Siemens A70 Service Repair Documentation page 28

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• DPRAM:
– Internal 16-bit dual port RAM with a 1K x 16-bit size.
• SCU (System Control Unit):
– Handles the boot and sleep mode of the core
– Provides a watchdog timer.
The architecture of the C166S combines the advantages of both RISC (Reduced Instruction
Set Computing) and CISC (Complex Instruction Set Computing) processors in a well-
balanced way. C166S based derivatives not only integrate a powerful MCU (Central
Processing Unit) core and a set of peripheral units into one chip, but also connects the units
in a very efficient way. One of the four buses used concurrently on the C166S is the Internal
Bus Interface, an internal representation of the external bus interface. This bus provides a
standardized method of integrating application-specific
peripherals to produce derivatives of the standard C166S.
The Principle Elements of a C166S Based System
• MCU block including the configurable Interrupt/PEC controller and debug and break logic
• Configurable dual port RAM
• Configurable Interrupt/PEC controller
• All interfaces for system (on chip) integration, including X-Bus, PD peripheral bus, Local
Memory bus (for ROM or SRAM).
The C166 architecture allows instruction execution and data access from all memory
locations. This includes X-Bus, local memory bus, dual port and external memories.
All four bus Interfaces of the MCU (X-Bus, LM Bus, RAM Bus and PD Bus) are operated
on at the same time by the MCU.
TEAKLite:
The TEAKLite core has 16-bit data and 16-bit program memory accesses, a high
performance fixed-point DSP core, and low power consumption.
The core consists of a high performance processing unit including a full featured bit-
manipulation unit, RAM and ROM addressing units, and program control logic. The core has
an improved set of DSP and general microprocessor functions to meet application
requirements. The programming model and instruction set are optimized for generation of
efficient and compact code.
The Computation Unit consists of a 16 by 16 multiplier unit with a 32-bit product and a 36-bit
ALU with two accumulator registers A0 and A1.
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