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Summary of Contents for Kontron VITA 57
- Page 1 VITA 57 Development Kit User's Guide SD.DT.F79-0e May 2011 If it's embedded, it's Kontron.
- Page 2 Initial Version May 2011 Copyright © 2011 Kontron AG. All rights reserved. All data is for information purposes only and not guaranteed for legal purposes. Information has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Kontron and the Kontron logo and all other trademarks or registered trademarks are the property of their respective owners and are recognized.
- Page 3 This document contains information proprietary to Kontron. It may not be copied or transmitted by any means, disclosed to others, or stored in any retrieval system or media without the prior written consent of Kontron or one of its authorized agents.
- Page 4 Therefore, in the interest of your own safety and of the correct operation of your new Kontron product, you are requested to conform with the following guidelines.
- Page 5 General Instructions on Usage In order to maintain Kontron’s product warranty, this product must not be altered or modified in any way. Changes or modifications to the device, which are not explicitly approved by Kontron and described in this manual or received from Kontron’s Technical Support as a special handling instruction, will void your warranty.
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Page 6: Table Of Contents
............FPGA Kontron Source Code . -
Page 7: Chapter 1 - Introduction
Linux distributions and are coded in C and python language. > Modifying some FPGA code IP’s like I2C, SPI is highly inadvisable. All modification will be done at customer’s own risks. I2C and SPI IPs were dedicated to Kontron boards so any changes could break some functionalities. Use cases This documents meet the following cases: >... -
Page 8: Chapter 2 - Development
FPGA image. FPGA Kontron Source Code The VITA 57 project example file tree is the following: The entry point of the Kontron source code is the file Topserial.v describing a VITA 57 implementation example. Page 2 SD.DT.F79-0e... - Page 9 The following shows the FPGA sources files: Now, you could add your Verilog files and libraries, modify the current files to match your application. You will find hereafter the snapshot of the VM6250 VITA 57 project as example. SD.DT.F79-0e Page 3...
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Page 10: Fpga Code Compilation
VITA 57 Development Kit User's Guide Development FPGA Code Compilation The following is an example of compilation based on VM6250 VITA 57 case. > You will find hereafter the snapshot of the VM6250 VITA 57 project as example: Page 4 SD.DT.F79-0e... - Page 11 VITA 57 Development Kit User's Guide Development > Open the ISE Design suite and select your project: > Select your application dedicated file into the hierarchy window (here, Topserial.v), then right click on “Generate program file” into the process window and click on “Run” or “ReRun” … to generate the “bit” or “bin”...
- Page 12 VITA 57 Development Kit User's Guide Development > The generation process is launched, if no errors appear, “bit” file will be generated into Worklib directory. Page 6 SD.DT.F79-0e...
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Page 13: Chapter 3 - Deployment
JTAG probe (see section 3.2 page 7). A tool is needed to convert mcs file to bin files that can be uploaded; refer to your platform VITA 57 BSP for more information. The flash... -
Page 14: Chapter 4 - Troubleshooting
> Boot the board and get the user and password from the VITA 57 BSP documentation of the board and log in. Configuration Check This is a basic verification of the installed software: # rpm −qa | grep VITA57... -
Page 15: Fmc Eeprom Check
VITA 57 Development Kit User's Guide Troubleshooting FMC EEPROM Check In order to access the FMC EEPROM run the following command to display the VPD: # e2fmc−v−W Product Name [My Board Product Name] Serial Number [My Board Serial Number] Part Number... - Page 16 VITA 57 Development Kit User's Guide Troubleshooting Set output GPIOs to 1: # gpio −c 9 −s GPIO_DataOut −v 0x2aa Check the GPIO levels: all must be at level 1 (because they are outputs at level 1, or because thay are inputs connected to the outputs).
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Page 17: Fmc Txn/Rxn Signals
VITA 57 Development Kit User's Guide Troubleshooting > it is also possible to set a register and read back the value of all registers in one command. For example the following lines : # gpio −c 9 −s GPIO_DataOut −v 0x2aa # gpio −c 9 −g GPIO_In... -
Page 18: 4.4.2.1 Enable Buffers
VITA 57 Development Kit User's Guide Troubleshooting 4.4.2.1 Enable buffers Set DXEN abd DXEN1516 as outputs: # gpio −c 8 −s GPIO_Control −v 0x3 Set DXEN and DXEN1516 to level 1 to enable all TXn outputs: # gpio −c 8 −s GPIO_DataOut −v 0x3 the command above is suitable for FMC-SER0 PCB B. - Page 19 VITA 57 Development Kit User's Guide Troubleshooting Check TX/RX signals when configured for RS422/485. The level set on TX1 must be also read on RX1, but setting a level on TX2 does not change RX2 as we are in differential mode: TX1/TX2 and RX1/RX2 are the same pair.
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Page 20: Low Level Debug With Io Command
VITA 57 Development Kit User's Guide Troubleshooting Low Level Debug with IO Command This command can be used to read/write FPGA registers. First, get the FPGA registers physical base address using "lspci -x": 0000:04:00.0 Memory controller: Teknor Industrial Computers Inc Unknown device... - Page 21 VITA 57 Development Kit User's Guide Troubleshooting Set TX1 to 0 − > should reread TX1 = 0, but also RX1 = 0 because of loopback [root@localhost ~]# io −4 −w 0x80000804 0x00000000 [root@localhost ~]# io −4 −r −l 0x4 0x80000808...
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Page 22: Chapter 5 - Additional Information
VITA 57 Development Kit User's Guide Additional Information Chapter 5 - Additional Information Loopback Connector on FMC-SER0 Front Panel This connector is to be plugged on the FMC-SER0 front panel connector to perform some tests on IOs and check that the hardware is OK. - Page 23 VITA 57 Development Kit User's Guide Additional Information Pin number Signal (50 pin connector) TX14 Already connected GPIO7 Already connected RX13 Already connected TX12 Already connected GPIO6 1Kohms to GPIO5 RX11 Already connected TX10 Already connected GPIO5 Already connected Already connected...
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Page 24: Io Routing With A Vm6250 Sbc Board As Fmc Carrier
VITA 57 Development Kit User's Guide Additional Information IO Routing with a VM6250 SBC board as FMC Carrier FPGA pin FMC-SER FMC-SER FMC-SER VM6250 VM6250 Test connector 0 signal 0 I/O name 0 signal to connector PMCB_IO VME P2 loopback... - Page 25 VITA 57 Development Kit User's Guide Additional Information FPGA pin FMC-SER FMC-SER FMC-SER VM6250 VM6250 Test connector 0 signal 0 I/O name 0 signal to connector PMCB_IO VME P2 loopback J14 pin pin from from VM6250 pin to signal connector...
- Page 26 VITA 57 Development Kit User's Guide Additional Information FPGA pin FMC-SER FMC-SER FMC-SER VM6250 VM6250 Test connector 0 signal 0 I/O name 0 signal to connector PMCB_IO VME P2 loopback J14 pin pin from from VM6250 pin to signal connector...
- Page 27 VITA 57 Development Kit User's Guide Additional Information With FMC-SER0 PCB B : these signals control TXn outputs of buffers (mandatory for RS485 mode) : level 1 : enabled level 0 : disabled - DXEN : TX1,TX2,TX3,TX4,TX5,TX6,TX7,TX8,TX9,TX10,TX11,TX12,TX13,TX14 - DXEN1516 : TX15/TX16 pair...
- Page 28 +33 (0) 4 98 16 34 00 150 rue Marcelin Berthelot - BP 244 sales@kontron.com ZI TOULON EST support-kom-sa@kontron.com 83078 TOULON CEDEX - France For further information about other Kontron products, please visit our Internet web site: www.kontron.com. If it's embedded, it's Kontron.
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