1. Manuals
  2. Brands
  3. Hynix Semiconductor Manuals
  4. Microcontrollers
  5. HMS81004E
  6. User manual

Hynix Semiconductor HMS81004E User Manual

8-bit single-chip microcontrollers
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
HYNIX SEMICONDUCTOR
8-BIT SINGLE-CHIP MICROCONTROLLERS
HMS81004/08/16/24/32E
HMS81020/32TL
User's Manual
(Ver. 2.00)

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the HMS81004E and is the answer not in the manual?

Questions and answers

Related Manuals for Hynix Semiconductor HMS81004E

Summary of Contents for Hynix Semiconductor HMS81004E

  • Page 1 HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS HMS81004/08/16/24/32E HMS81020/32TL User’s Manual (Ver. 2.00)
  • Page 2 Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

  • Page 3: Table Of Contents

    HMS81032E/HMS81032TL 1. OVERVIEW..........1 14. INTERRUPTS ........46 Description ............1 Interrupt priority and sources ......47 Features ............1 Interrupt control register ........ 47 Development Tools ..........2 Interrupt accept mode ........48 Interrupt Sequence ........49 2. BLOCK DIAGRAM .......3 BRK Interrupt ..........51 Multi Interrupt ..........
  • Page 4 HMS81032E/HMS81032TL NOV 2001 Ver 2.00...

  • Page 5: Overview

    The HMS81004E/08E/16E/24E/32E is an advanced CMOS 8-bit microcontroller with 4/8/16/24/32K bytes of ROM. The device is one of GMS800 family. The HYNIX HMS81004E/08E/16E/24E/32E is a powerful microcontroller which provides a highly flexible and cost effective solution to many UR applications.The HMS81004E/08E/16E/24E/32E provides the fol- lowing standard features: 4/8/16/24/32K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, on-chip oscillator and clock circuitry.

  • Page 6: Development Tools

    HMS81032E/HMS81032TL 1.3 Development Tools The HMS81004E/08E/16E/24E/32E are supported by a full-fea- - MS- Window base assembler tured macro assembler, an in-circuit emulator CHOICE-Dr. Software - Linker / Editor / Debugger and OTP programmers. Macro assembler operates under the MS- Windows 95/98 /NT4/W2000.

  • Page 7: Block Diagram

    HMS8132E/HMS81032TL 2. BLOCK DIAGRAM G8MC Core R00~R07 Watchdog PORT Timer REMOUT (448byte) R17/T0 Timer R16/T1 R15/T2 R14/EC R10~R17 PORT R12/INT2 Interrupt R11/INT1 (32kbyte) Key Scan R00~R07 INT. R10~R17 Generation Block R20~R24 PORT TEST Clock Gen. Prescaler & & RESET System B.I.T Control XOUT...

  • Page 8: Pin Assignment (Top View)

    HMS81032E/HMS81032TL 3. PIN ASSIGNMENT (Top View) REMOUT REMOUT REMOUT XOUT RESET XOUT XOUT RESET RESET 24PIN TEST 28PIN TEST TEST 20PIN Nov. 2001 Ver 2.00...

  • Page 9: Package Dimension

    HMS8132E/HMS81032TL 4. PACKAGE DIMENSION 20 SOP UNIT: INCH 0.512 0.495 0 ~ 8° 0.020 0.042 0.013 0.050 BSC 0.016 20 PDIP 0.300 BSC 1.043 1.015 0.270 0.245 MAX 0.180 MIN 0.015 0.021 0 ~ 15° 0.100 BSC 0.015 0.065 0.050 Nov.
  • Page 10 HMS81032E/HMS81032TL 24 SOP UNIT: INCH 0.614 0.598 0 ~ 8° 0.020 0.042 0.013 0.050 BSC 0.016 24 SKDIP 0.300 BSC 1.265 1.160 0.300 0.250 MAX 0.180 MIN 0.015 0.021 0.100 BSC 0 ~ 15° 0.015 0.065 0.045 Nov. 2001 Ver 2.00...
  • Page 11 HMS8132E/HMS81032TL 28 SOP UNIT: INCH 0.713 0.697 0 ~ 8° 0.020 0.042 0.013 0.050 BSC 0.016 28 SKDIP 0.300 BSC 1.375 1.355 0.300 0.275 MAX 0.180 MIN 0.020 0.021 0.100 BSC 0 ~ 15° 0.015 0.055 0.045 Nov. 2001 Ver 2.00...

  • Page 12: Pin Function

    HMS81032E/HMS81032TL 5. PIN FUNCTION : Supply voltage. used as outputs or inputs. : Circuit ground. In addition, R1 serves the functions of the various follow- ing special features. TEST: Used for shipping inspection of the IC. For normal operation, it should be connected to V Port pin Alternate function RESET: Reset the MCU.
  • Page 13 HMS8132E/HMS81032TL INPUT/ PIN NAME Function @RESET @STOP OUTPUT - Each bit of the port can be individually configured as an input or an output by user software - Push-pull output State of - CMOS input with pull-up resister (option) INPUT before - Can be programmable as key scan input Stop...

  • Page 14: Port Structures

    HMS81032E/HMS81032TL 6. PORT STRUCTURES R0[0:7] R11/INT1, R12/INT2, R14/EC OTP: connected MASK: option (default connected) OTP: connected Circuit MASK: option (default connected) Pull up Circuit Pull-up Tr. Reg. Pull up Pull-up Tr. Open Drain Reg. Reg. Open Drain Reg. Data Reg. Data Reg.
  • Page 15 HMS8132E/HMS81032TL R15/T2, R16/T1, R17/T0 TEST OTP: connected MASK: option (default connected) Circuit Noise Pull up Pull-up Tr. Filter Reg. Open Drain Reg. REMOUT Data Reg. Function Sele- ction Reg. Internal Signal Dir R eg. XIN, XOUT to R15...T2 to R16...T1 to R17...T0 Key Scan Input...

  • Page 16: Electrical Characteristics

    HMS81032E/HMS81032TL 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Supply voltage ........... -0.3 to +4.1 V Note: Stresses above those listed under “Absolute Maxi- Input Voltage ........-0.3 to V +0.3 V mum Ratings” may cause permanent damage to the de- vice. This is a stress rating only and functional operation of Output Voltage ........-0.3 to V +0.3 V the device at any other conditions above those indicated in...

  • Page 17: Remout Port Ioh Characteristics Graph

    HMS8132E/HMS81032TL Specifications Parameter Symbol Condition Unit Min. Typ. Max. High Level REMOUT, V output current Low Level REMOUT, V output current µA Input pull-up current R0,R1,R2, RESET, VDD=3V Operating current, fxin=4Mhz, VDD=2.0V Operating current, fxin=4Mhz, VDD=3.6V Sleep mode current, fxin=4Mhz, SLP1 VDD=2.0V Sleep mode current, fxin=4Mhz,...

  • Page 18: Remout Port Iol Characteristics Graph

    HMS81032E/HMS81032TL 7.5 REMOUT Port Iol Characteristics Graph (typical process & room temperature) Iol(mA) Vdd 4V Vdd 3V Vdd 2V Vol (V) Figure 7-2 Iol vs Vol 7.6 AC Characteristics =0~+70° ° ° ° C, V =2.0~3.6V =0V) Specifications Parameter Symbol Pins Unit Min.
  • Page 19 HMS8132E/HMS81032TL -0.5V 0.5V INT1 0.8V INT2 0.2V RSTL RESET 0.2V 0.8V 0.2V Figure 7-3 Timing Diagram Nov. 2001 Ver 2.00...

  • Page 20: Memory Organization

    HMS81032E/HMS81032TL 8. MEMORY ORGANIZATION The HMS81004E/08E/16E/24E/32E has separate address 32K bytes of Program memory. Data memory can be read spaces for Program memory and Data Memory. Program and written to up to 448 bytes including the stack area. memory can only be read, not written to. It can be up to 8.1 Registers...
  • Page 21 HMS8132E/HMS81032TL Caution: Stack Address (100 ~ 1FF The Stack Pointer must be initialized by software be- cause its value is undefined after RESET. Example: To initialize the SP #0FFH Hardware fixed ; SP ← FF TXSP At execution of At acceptance At execution At execution a CALL/TCALL/PCALL...
  • Page 22 HMS81032E/HMS81032TL [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. RESET VALUE: 00 CARRY FLAG RECEIVES NEGATIVE FLAG CARRY OUT OVERFLOW FLAG ZERO FLAG SELECT DIRECT PAGE INTERRUPT ENABLE FLAG when g=1, page is addressed by RPR...

  • Page 23: Program Memory

    HMS8132E/HMS81032TL 8.2 Program Memory A 16-bit program counter is capable of addressing up to Example: Usage of TCALL 64K bytes, but this device has 4/8/16/24/32K bytes pro- gram memory space only physically implemented. Ac- ;1BYTE INSTR UCTIO N TCALL 0FH cessing a location above FFFF will cause a wrap-around ;INSTEAD OF 2 BYTES...
  • Page 24 HMS81032E/HMS81032TL Address Program Memory 0FFC0 TCALL 15 TCALL 14 TCALL 13 Address PCALL Area Memory TCALL 12 0FF00 TCALL 11 PCALL Area TCALL 10 (192 Bytes) TCALL 9 TCALL 8 0FFBF TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK *...
  • Page 25 HMS8132E/HMS81032TL Example: The usage software example of Vector address and the initialize part. 0FFE0H NOT_USED NOT_USED NOT_USED BIT_INT ; BIT WDT_INT ; Watch Dog Timer NOT_USED NOT_USED TMR2_INT ; Timer-2 TMR1_INT ; Timer-1 TMR0_INT ; Timer-0 NOT_USED INT2 ; Int.2 INT1 ;...

  • Page 26: Data Memory

    User Memory return instruction [RETI] restores the contents of the pro- The HMS81004E/08E/16E/24E/32E has 448 × 8 bits for gram counter and flags. the user memory (RAM). The save/restore locations in the stack are determined by Control Registers the stack pointed (SP).

  • Page 27: List For Control Registers

    HMS8132E/HMS81032TL 8.4 List for Control Registers Read Address Function Register Symbol RESET Value Write 00C0h PORT R0 DATA REG. undefined 00C1h PORT R0 DATA DIRECTION REG. R0DD 00000000b 00C2h PORT R1 DATA REG. undefined 00C3h PORT R1 DATA DIRECTION REG. R1DD 00000000b 00C4h...
  • Page 28 HMS81032E/HMS81032TL 00DFh PORT R2 OPEN DRAIN ASSIGN REG. R2ODC 00000000b 00E0h Reserved 00E1h Reserved 00E2h Reserved 00E3h Reserved 00E4h PORT R0 OPEN DRAIN ASSIGN REG. R0ODC 00000000b 00E5h Reserved 00E6h Reserved 00E7h Reserved 00E8h Reserved 00E9h Reserved 00EAh Reserved 00EBh Reserved 00ECh Reserved...

  • Page 29: Addressing Mode

    HMS8132E/HMS81032TL 8.5 Addressing Mode The HMS81004E/08E/16E/24E/32E uses six addressing E45535 35H,#55H modes; • Register addressing • Immediate addressing data ← 55H data 0C35 • Direct page addressing • Absolute addressing • Indexed addressing 0F100 0F101 • Register-indirect addressing 0F102 (1) Register Addressing Register addressing accesses the A, X, Y, C and PSW.
  • Page 30 HMS81032E/HMS81032TL 0735F0 !0F035H ;A←ROM[0F035H] ;ACC←RAM[X]. data 0F035 data data → A A+data+C → A 0F100 0E550 0F101 address: 0F035 0F102 X indexed direct page, auto increment→ → → → {X}+ The operation within data memory (RAM) In this mode, a address is specified within direct page by ASL, BIT, DEC, INC, LSR, ROL, ROR the X register and the content of X is increased by 1.
  • Page 31 HMS8132E/HMS81032TL JMP, CALL C645 45H+X Example; G=0 3F35 [35H] data data → A 0E550 0E551 45H+0F5H=13AH jump to address 0E30A 0E30A NEXT Y indexed direct page (8 bit offset) → → → → dp+Y 0FA00 This address value is the second byte (Operand) of com- mand plus the data of Y-register, which assigns Memory in Direct page.
  • Page 32 HMS81032E/HMS81032TL Y indexed indirect → → → → [dp]+Y Absolute indirect → → → → [!abs] Processes memory data as Data, assigned by the data The program jumps to address specified by 16-bit absolute [dp+1][dp] of 16-bit pair memory paired by Operand in Di- address.

  • Page 33: I/O Ports

    HMS8132E/HMS81032TL 9. I/O PORTS (1) R0 I/O Data Direction Register (R0DD) The HMS81004E/08E/16E/24E/32E has 24 I/O ports which are PORT0(8 I/O), PORT1 (8 I/O), PORT2 (8 I/O). R0 I/O Data Direction Register (R0DD) is 8-bit register, Pull-up resistor of each port can be selectable by program.
  • Page 34 HMS81032E/HMS81032TL and can assign R1 port as open drain output port each bit, if corresponding port is selected as output. If R1ODC is se- ADDRESS: 0C2 R1 Data Register (R/W) lected as “1”, port R1 is open drain output, and if selected RESET VALUE: Undefined as “0”, it is push-pull output.

  • Page 35: R2 Port

    HMS8132E/HMS81032TL pull-up is automatically disabled, if corresponding port is (1) R2 I/O Data Direction Register (R2DD) selected as output. R2 I/O Data Direction Register (R2DD) is 8-bit register, and can assign input state or output state to each bit. If R2DD is “1”, port R2 is in the output state, and if “0”, it is in the input state.

  • Page 36: Clock Generator

    HMS81032E/HMS81032TL 10. CLOCK GENERATOR Clock generating circuit consists of Clock Pulse Generator state. (C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch Dog Timer. The clock applied to the Xin pin divided by ADDRESS: 0C7 Clock Control Register (W) INITIAL VALUE: --110111b two is used as the internal system clock.

  • Page 37: Oscillation Circuit

    HMS8132E/HMS81032TL 10.1 Oscillation Circuit Oscillation circuit is designed to be used either with a ce- Oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. Figure 10-2 shows ramic resonator or crystal oscillator. Since each crystal and circuit diagrams using a crystal (or ceramic) oscillator.
  • Page 38 HMS81032E/HMS81032TL Frequency Resonator Maker Part Name Load Capacitor Operating Voltage ZTT2.00 Cin=Cout=open 2.0~3.6 ZTA2.00 Cin=Cout=30pF 2.0~3.6 2.00MHz MURATA CSTLS2M00G56-B0 Cin=Cout=open 2.0~3.6 MURATA CSTCC2.00MG0H6 Cin=Cout=open 2.0~3.6 MURATA CSTCC2M00G56-R0 Cin=Cout=open 2.0~3.6 ZTT4.00 Cin=Cout=open 2.0~3.6 ZTA4.00 Cin=Cout=30pF 2.0~3.6 MURATA CSTS0400MG06 Cin=Cout=open 2.0~3.6 MURATA CSTLS4M00G56-B0 Cin=Cout=open 2.0~3.6...

  • Page 39: Basic Interval Timer

    HMS8132E/HMS81032TL 11. BASIC INTERVAL TIMER The HMS81004E/08E/16E/24E/32E has one 8-bit Basic The Basic Interval Timer is controlled by the clock control Interval Timer that is free-run and can not stop. Block dia- register (CKCTLR) shown in Figure 11-2. If bit3(BTCL) gram is shown in Figure 11-1.
  • Page 40 HMS81032E/HMS81032TL ADDRESS: 0C7 CKCTLR BTCL BTS2 BTS1 BTS0 WDTON ENPCK BTCL INITAIL VALUE: --110111 Basic Interval Timer source clock select ÷ 000: f ÷ 001: f ÷ 010: f ÷ 011: f ÷ 100: f ÷ 101: f ÷ 110: f Caution: ÷...

  • Page 41: Watch Dog Timer

    HMS8132E/HMS81032TL 12. WATCH DOG TIMER Watch Dog Timer (WDT) consists of 6-bit binary counter, As IFBIT (Basic Interval Timer Interrupt Request) is used 6-bit comparator, and Watch Dog Timer Register for input clock of WDT, Input clock cycle is possible from (WDTR).Watch Dog Timer can be used 6-bit general Tim- 512 us to 65,536 us by BTS.

  • Page 42: Timer0, Timer1, Timer2

    HMS81032E/HMS81032TL 13. Timer0, Timer1, Timer2 (1) Timer Operation Mode Register (T1LD), Timer2 Data Register (T2DR). Any of the PS0 ~ PS5, PS11 and external event input EC can be Timer consists of 16bit binary counter Timer0 (T0), 8bit selected as clock source for T0. Any of the PS0 ~ PS3, PS7 binary Timer1 (T1), Timer2 (T2), Timer Data Register, ~ PS10 can be selected as clock T1.
  • Page 43 HMS8132E/HMS81032TL T0HMD T0HLD T0LMD T0LLD T1HD T1LD T2DR from EC/R14 Timer0 (16bit) Timer2(8bit) Timer1(8bit) TM01 T0IN IT T1INIT TO U TS TO UTB T0O UTP BTC L TO UT1 TO UT0 Edge Polarity Tout Selection Selection Logic from INT2/R12 (Capture Signal) T2OUT T0OUT TOUT...
  • Page 44 HMS81032E/HMS81032TL IEDS[5:4] INT2 INT2/R12 PIN IFINT2 INTERRUPT 16 BITS T0HC T0LC [0D5 ][0D6 capture T0ST CAP0 T0IFS T 0 S L [2 :0 ] E d g e D e te cto r delay EC PIN 1 1 1 Interrupt CAP0 clear IFT0...
  • Page 45 HMS8132E/HMS81032TL T1ST T1IFS T1 COUNT REG. T 1S L [2 :0 ] [0D8 P S 1 0 Interrupt 1 11 IFT1 P S 9 GEN. 1 10 clear P S 8 1 01 T1 COUNTER (8-bit) P S 7 1 00 P S 3 0 11 OUTPUT...
  • Page 46 HMS81032E/HMS81032TL T2ST T2 COUNT REG. T 2S L [2 :0 ] [0D9 P S 1 2 Interrupt 1 11 IFT2 P S 1 1 GEN. 1 10 clear P S 1 0 1 01 T2 COUNTER (8-bit) P S 9 1 00 P S 8 0 11...
  • Page 47 HMS8132E/HMS81032TL 2) Timer0, Timer1 TIMER0 and TIMER1 have an up-counter. When value of (TDR), the up-counter is cleared to “00h”, and interrupt the up-counter reaches the content of Timer Data Register (IFT0, IFT1) is occurred at the next clock. T0 Data MATCH Register (TDR = T0)
  • Page 48 HMS81032E/HMS81032TL enable disable clear & start stop TIME Timer 0 (IFT0) Interrupt Occur interrupt Occur interrupt T0ST T0ST = 1 Start & Stop T0ST = 0 T0CN T0CN = 1 Control count T0CN = 0 Figure 13-6 Start/Stop Operation of Timer0 INT2 Figure 13-7 Input capture operation of Timer0 Nov.
  • Page 49 HMS8132E/HMS81032TL 3) Single/Modulo-N Mode Timer0 (Timer1) can select initial (T0INIT, T1INIT of should be set “0”. Counter counts up until the value of Data TM01) output level of Timer Output port. If initial level is Register and occurs Time-out interrupt. The level of Timer “L”, Low-Data Register value of Timer Data Register is Output port toggle and repeats process of transferred to comparator and T0OUT (T1OUT) is to be...

  • Page 50: Interrupts

    - Nested interrupt control is possible uration of interrupt circuit is shown in Figure 14-1. - Programmable interrupt mode The HMS81004E/08E/16E/24E/32E contains 8 interrupt (Hardware and software interrupt accept mode) sources; 3 externals and 5 internals. Nested interrupt ser- - Read and write of interrupt request flag are possible.

  • Page 51: Interrupt Priority And Sources

    HMS8132E/HMS81032TL 14.1 Interrupt priority and sources Each interrupt vector is independent and has its own pri- source classification is shown in Table 14-1. ority. Software interrupt (BRK) is also available. Interrupt 14.2 Interrupt control register I flag of PSW is a interrupt mask enable flag. When I flag during interrupt cycle process.

  • Page 52: Interrupt Accept Mode

    HMS81032E/HMS81032TL ADDRESS: 0CC WDTE BITE IENL INITIAL VALUE: -00- ---- Watchdog timer Basic Interval Timer VALUE 0: Disable ADDRESS: 0CE IENH KSCNE 1: Enable INT1E INT2E INITIAL VALUE: 000- 000- Key scan Timer2 External interrupt 1 Timer1 External interrupt 2 Timer0 ADDRESS: 0CD BITR...

  • Page 53: Interrupt Sequence

    HMS8132E/HMS81032TL Interrupt mode register ADDRESS: 0CA IMOD IM 1 IM 0 BTCL IP 3 IP 2 INITIAL VALUE: --000000 Priority Selection interrupt 00: Fixed by hardware 0001: KSCNR 01: Changeable by IP3~IP0 0010: INT1R 1x: Interrupt is inhibited 0011: INT2R 0101: T0R 0110: T1R 0111: T2R...
  • Page 54 HMS81032E/HMS81032TL System clock Instruction Fetch SP-2 V.L. V.H. New PC SP-1 Address Bus Not used V.L. OP code Data Bus Internal Read Internal Write Interrupt Processing Step Interrupt Service Task V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents. Figure 14-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself.

  • Page 55: Brk Interrupt

    HMS8132E/HMS81032TL However, multiple processing through software for special fea- tures is possible. Generally when an interrupt is accepted, the I- flag is cleared to disable any further interrupt. But as user sets I- main task flag in interrupt routine, some further interrupt can be serviced acceptance of interrupt interrupt...

  • Page 56: Key Scan Input Processing

    HMS81032E/HMS81032TL INT1 pin IFINT1 INT1 INTERRUPT INT2 pin IFINT2 INT2 INTERRUPT Edge selection IEDS Register [0CBH] Ext. Int. Edge Selection reg. ADDRESS: 0CB IEDS IED2H IED 2L IE D1H IED1L BTCL INITIAL VALUE: --0000-- IED2* IED1* 01: Falling Edge Selection 01: Falling Edge Selection 10: Rising Edge Selection 10: Rising Edge Selection...
  • Page 57 HMS8132E/HMS81032TL Standby release level control register (SRLC) can select (SRLC) is write-only register and initialized as “00h” in re- the key scan input level “L” or “H” for standby release by set state. each bit pin (R0, R1). Standby release level control register SMRR0 SRLC0 R 0 0...

  • Page 58: Standby Function

    HMS81032E/HMS81032TL 15. STANDBY FUNCTION 15.1 Sleep Mode SLEEP mode can be entered by setting the bit of SLEEP mode register (SLPM). In the mode, CPU clock stops but oscillator keeps running. B.I.T and a part of peripheral ADDRESS: 0F0 Sleep Mode Control Register (W) INITIAL VALUE: -------0b hardware execute, but prescaler output which provide SLPM...

  • Page 59: Standby Mode Release

    HMS8132E/HMS81032TL Clock Pulse CPU Clock Generator Circuit Basic Interval Timer Prescaler Clear Clear Control Signal STOP Overflow Detection Release Signal from Interrupt RESETB Figure 15-1 Block Diagram of Standby Circuit 15.3 Standby mode release Release of STANDBY mode is executed by RESET input and Interrupt signal.
  • Page 60 HMS81032E/HMS81032TL Release Factor Release Method RESETB By RESETB Pin=Low level, Standby mode is released and system is initialized Standby mode is released by low input of selected pin by key scan Input(SMRR0,SMRR1). KSCN(Key Input) In case of interrupt mask enable flag= “0”, program executes just after standby instruction, if flag= “1”...

  • Page 61: Operation Of Standby Mode Release

    HMS8132E/HMS81032TL 15.4 Operation of standby mode release After standby mode is released, the operation begins ac- standby mode start (Figure 15-3). cording to content of related interrupt register just before STOP Command Standby Mode Interrupt Request GEN. Int. enable reg. Standby Mode Release I Flag Standby Next Command...
  • Page 62 HMS81032E/HMS81032TL Internal circuit SLEEP mode STOP mode Oscillator Active Stop Internal CPU Stop Stop Register Retained Retained Retained Retained I/O port Retained Retained Prescaler Active Stop PS10 selected:Active Basic Interval Timer Stop Others: Stop Watch-dog Timer Stop Stop Timer Stop Stop Address Bus,Data Bus Retained...

  • Page 63: Reset Function

    HMS8132E/HMS81032TL 16. RESET FUNCTION 16.1 External RESET The RESET pin should be held at low for at least 2machine stable system initialization. The RESET pin contains a cycles with the power supply voltage within the operating Schmitt trigger with an internal pull-up resistor. voltage range and must be connected 0.1uF capacitor for RESET 0.1uF capacitor...
  • Page 64 HMS81032E/HMS81032TL Internal Reset RESET Noise Filter 0.1uF Power on Detect Pulse Generator Clear Clear Clear B.I.T. Basic PS10 Overflow Interval Prescaler Circuit Detection Timer Circuit Figure 16-2 Block Diagram of Power On Reset Circuit Note: When Power On Reset, oscillator stabilization time doesn`t include OSC.

  • Page 65: Low Voltage Detection Mode

    HMS8132E/HMS81032TL Oscillator pin) RESET ADDRESS FFFE FFFF Start DATA MAIN PROGRAM RESET Process Step Stabilization Time ADL and ADH are start addresses of interrupt service routine as vector contents. Figure 16-4 Timing Diagram of Reset 16.3 Low voltage detection mode (1) Low voltage detection condition all port can be selected with Pull-up resistor by Mask op- tion.
  • Page 66 HMS81032E/HMS81032TL (4) SRAM BACK-UP after Low Voltage Detection. about hours depend on Vdd-GND Capacitor SRAM Data Backup Low Voltage detection point 2V(Min.) 1.7V(typ.20 °C) Power on Reset (SRAM retention) 0.7V(Vret) Power on Reset (SRAM unstable) Time User replaces User removes batteries batteries Figure 16-6 Oscillator stabilizing diagram...
  • Page 67 HMS8132E/HMS81032TL (5) S/W flow chart example after Reset using SRAM Back-up RESET Stack Pointer initialize Check the SRAM value (RAM Pattern, Checksum) SRAM DATA VALID? Clear all Ram area Use Saved SRAM value Main routine Figure 16-7 S/W flow chart example after Reset using SRAM Back-up Nov.

  • Page 68: Overview Of Hms81032Tl

    HMS81032E/HMS81032TL 17. OVERVIEW OF HMS81032TL 17.1 Standard Mode pin assignment 24Pin REMOUT REMOUT 28Pin (300mil width XOUT RESET XOUT RESET (300mil width PDIP & SOP) TEST TEST PDIP & SOP) 39 38 37 36 35 34 33 32 31 30 29 REMOUT XOUT RESET...

  • Page 69: Prom Mode Pin Assignment

    HMS8132E/HMS81032TL 17.2 PROM Mode pin assignment No Connect No Connect No Connect No Connect AL   WE AH   VE  RDE VDD   VSS VDD  VSS   VPP 28Pin A0 / A8 / D0   D7 / A15 / A7 A1 / A9 / D1   D6 / A14 / A6...

  • Page 70: Standard Mode Pin Desciption

    HMS81032E/HMS81032TL 17.3 Standard Mode Pin Desciption Pin Number Input Output Function @ RESET @ STOP Name Type 20Pin 24Pin 28Pin 44Pin  8bit CMOS input with pull_up resistor (option).  8bit push-pull output. Input  During output, pull-up resistor Input Remain Output is disabled automatically.

  • Page 71: Prom Mode Pin Description

    HMS8132E/HMS81032TL 17.4 PROM Mode Pin Description Standard EPROM Input 28Pin Mode Mode Output Function Number Pin Name Pin Name Type No Connection No Connection Input Address Low Input Enable Input Address High Input Enable Power Positive Power Supply XOUT Power Power Ground A0/A8/D0...

  • Page 72: Eprom Mode

    HMS81032E/HMS81032TL 17.5 EPROM Mode Mode setting during power up Mode setting PROM Write & Verify 11.5V PROM Verify or Read 11.5V LOCK Bit Write 11.5V LOCK Bit Read 11.5V ROM Size Write 11.5V ROM Size Read 11.5V Mode setting after power up Mode setting Remark Address High Latch...
  • Page 73 HMS8132E/HMS81032TL Programming DC charateristics Items Symbol Min. Typ. Max. Unit Test condition Input high voltage VDD+0.3 Input low voltage -0.1 Output high voltage IOH=-2.5mA Output low voltage IOL=1mA VDD current VPP current W E=VIL VDD voltage VPP voltage 11.2 11.5 11.8 VSS voltage GROUND Level...
  • Page 74 HMS81032E/HMS81032TL Verify or Read DC characteristics (Vdd=5.0V±0.5V, Vpp=11.5V±0.3V, Vss=0V, Ta=25±5 °C) Items Symbol Min. Typ. Max. Unit Test condition VDD Active current IDD1 VE=VIL Input high voltage VDD-0.2 VDD+0.2 Input low voltage -0.2 Output high voltage 0.7VDD IOH=-2.5mA Output low voltage IOL=1mA Verify or Read AC characteristics (Vdd=5.0V±0.5V, Vpp=11.5V±0.3V, Vss=0V, Ta=25±5 °C)

  • Page 75: Timing Diagram In Eprom Mode

    HMS8132E/HMS81032TL 17.6 Timing Diagram in EPROM Mode EPROM Write & Verify (VDD) Min. 50ms 11.5V (TESTB) (RESETB) (REMOUT) Min. Min. Latch Timing 10us (R10) Latch Timing (R11) (R16) (R17) (R20) DOUT [7:0] Mode setting 1Byte PGM Verify Repeat area  1. R0[7:0] address input is latched when AH(R10), AL(R11) is rising. 2.
  • Page 76 HMS81032E/HMS81032TL EPROM Verify or Read (VDD) Min. 50ms 11.5V (TESTB) (RESETB) (REMOUT) Min. Min. Latch Timing 10us (R10) Latch Timing (R11) (R16) (R17) (R20) DOUT [7:0] Mode setting Verify  AH : High Byte Address Input AL : Low Byte Address Input DIN : Data Input DOUT : Data Output Nov.
  • Page 77 HMS8132E/HMS81032TL Lock Bit Write (VDD) Min. 50ms 11.5V (TESTB) (RESETB) (REMOUT) Min. Min. Latch Timing 10us (R10) (R11) (R16) (R17) (R20) DIN ( 06XH ) [7:0] Mode setting  1. DIN = 06XH : LOCK bit Write Data. ( X means “don’t care” ) Writing time (R16 is `Low`) is 200us, and can not verify locked or not in this mode.
  • Page 78 HMS81032E/HMS81032TL LOCK Bit Read (VDD) Min. 50ms 11.5V (TESTB) (RESETB) (REMOUT) Min. Min. Latch Timing 10us (R10) (R11) (R16) (R17) (R20) DOUT [7:0] Mode setting Lock bit Read LOCK bit read Normal Locked Nov. 2001 Ver 2.00...

  • Page 79: Programming Flow Chart

    HMS8132E/HMS81032TL 17.7 Programming Flow Chart Start Set EPROM write to wirte/verify mode. VDD = 5V  0.5V VPP = 11.5V  0.3V Start Address n = 0 n + 1  n N  20 ? WE = 200us  10% Data write : Fail Verify...

  • Page 80: Remout Port Ioh Characteristics Graph

    HMS81032E/HMS81032TL 17.8 REMOUT Port Ioh Characteristics Graph (typical process & room temperature) Ioh(mA) Vdd 2V Vdd 3V Vdd 4V Voh (V) Figure 17-3 Ioh vs Voh 17.9 REMOUT Port Iol Characteristics Graph (typical process & room temperature) Iol(mA) Vdd 4V Vdd 3V Vdd 2V Vol (V)
  • Page 81 HMS8132E/HMS81032TL LVD(V) -20 -15 Temperature (°C) Figure 17-5 Low Voltage vs Temperature Nov. 2001 Ver 2.00...

  • Page 82: General Circuit Diagram

    HMS81032E/HMS81032TL 18. GENERAL CIRCUIT DIAGRAM 18.1 General circuit diagram of HMS81032E In case of using high gain Tr for longer transmission distance application. We recommend to attach proper value of capacitor between REMOUT pin of chip and VSS of system to prevent excessive overshoot voltage of system power (over the maximum supply VCC of chip) during signal transmission.

  • Page 83: General Circuit Diagram Of Hms81032Tl

    HMS8132E/HMS81032TL 18.2 General circuit diagram of HMS81032TL H M S 81 03 2T L R 14 R 1 3 Infrared L E D R 15 R 1 2 R 16 R 1 1 R 17 R 1 0 V D D R E M O U T 0.1u F R E SE T...
  • Page 84 HMS81032E/HMS81032TL Nov. 2001 Ver 2.00...
  • Page 85 APPENDIX...

  • Page 86: Mask Order Sheet

    A. MASK ORDER SHEET MASK ORDER & VERIFICATION SHEET E -UE HMS810 Customer should write inside thick line box. 1. Customer Information 2. Device Information 20SOP 20PDIP Company Name 24SOP 24SKDIP Application Package 28SOP YYYY 28SKDIP Order Date 28PIN DIE Tel: Fax: Mask Data...

  • Page 87: Instruction

    APPENDIX B. INSTRUCTION B.1 Terminology List Terminology Description Accumulator X - register Y - register Program Status Word #imm 8-bit Immediate data Direct Page Offset Address !abs Absolute Address Indirect expression Register Indirect expression { }+ Register Indirect expression, after that, Register auto-increment .bit Bit Position A.bit...

  • Page 88: Instruction Map

    APPENDIX B.2 Instruction Map 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 HIGH SET1 TCALL SETA1 PUSH dp.bit A.bit,rel dp.bit,rel #imm dp+X !abs .bit TCALL CLRA1 PUSH CLRC #imm dp+X !abs .bit TCALL NOT1 PUSH...

  • Page 89: Instruction Set

    APPENDIX B.3 Instruction Set Arithmetic / Logic Operation Byte Cycle Flag Mnemonic Operation Code NVGBHIZC ADC #imm Add with carry. A ← ( A ) + ( M ) + C ADC dp ADC dp + X ADC !abs NV--H-ZC ADC !abs + Y ADC [ dp + X ] ADC [ dp ] + Y...
  • Page 90 APPENDIX Byte Cycle Flag Mnemonic Operation Code NVGBHIZC Divide : YA / X Q: A, R: Y NV--H-Z- EOR #imm Exclusive OR A ← ( A ) ⊕ ( M ) EOR dp EOR dp + X EOR !abs N-----Z- EOR !abs + Y EOR [ dp + X ] EOR [ dp ] + Y...
  • Page 91 APPENDIX Register / Memory Operation Byte Cycle Flag Mnemonic Operation Code NVGBHIZC LDA #imm Load accumulator A ← ( M ) LDA dp LDA dp + X LDA !abs LDA !abs + Y N-----Z- LDA [ dp + X ] LDA [ dp ] + Y LDA { X } X- register auto-increment : A ←...
  • Page 92 APPENDIX 16-BIT operation Byte Cycle Flag Mnemonic Operation Code NVGBHIZC 16-Bits add without Carry ADDW dp NV--H-ZC YA ← ( YA ) ( dp +1 ) ( dp ) Compare YA contents with memory pair contents : CMPW dp N-----ZC (YA) −...
  • Page 93 APPENDIX Branch / Jump Operation Byte Cycle Flag Mnemonic Operation Code NVGBHIZC BBC A.bit,rel Branch if bit clear : -------- if ( bit ) = 0 , then pc ← ( pc ) + rel BBC dp.bit,rel BBS A.bit,rel Branch if bit set : -------- if ( bit ) = 1 , then pc ←...
  • Page 94 APPENDIX Control Operation & Etc. Byte Cycle Flag Mnemonic Operation Code NVGBHIZC Software interrupt : B ← ”1”, M(sp) ← (pc ), sp ←sp-1, M(s) ← (pc ), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, ---1-0-- ←...

This manual is also suitable for:

Hms81008eHms81016eHms81024eHms81032eHms81020tlHms81032tl

Table of Contents