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Hynix Semiconductor GMS81C5108 User Manual

8-bit single-chip microcontrollers
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HYNIX SEMICONDUCTOR INC.
8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS81C5108
User's Manual (Ver. 1.0)
Downloaded from
Elcodis.com
electronic components distributor

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Summary of Contents for Hynix Semiconductor GMS81C5108

  • Page 1 HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS GMS81C5108 User’s Manual (Ver. 1.0) Downloaded from Elcodis.com electronic components distributor...
  • Page 2 MCU Application Team © © © © 20 20 20 200 0 0 0 1 1 1 1 Hynix Semiconductor Inc. All rights reserved. Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Repre- sentatives listed at address directory.

  • Page 3: Table Of Contents

    GMS81C5108 Table of Contents 1. OVERVIEW ...........1 8-Bit Capture Mode ......... 50 16-bit Capture Mode ........53 Description ............1 8-Bit (16-Bit) Compare OutPut Mode ....53 Features .............1 PWM Mode ............. 53 Development Tools ..........2 Ordering Information 13. Watch Timer/Watch Dog Timer..56 2.

  • Page 4: Overview

    1.1 Description The GMS81C5108 is an advanced CMOS 8-bit microcontroller with 8K bytes of ROM. The device is one of GMS800 fam- ily. The Hynix GMS81C5108 is a powerful microcontroller which provides a high flexibility and cost effective solution to many LCD applications.

  • Page 5: Development Tools

    - CHOICE - SIGMA (Single writer) OTP Writer - CHOICE - GANG4 (Gang writer) The GMS81C5108 is supported by a full-featured macro assem- bler, an in-circuit emulator CHOICE-Dr. and OTP program- mers. There are two different type programmers such as single type and gang type.

  • Page 6: Block Diagram

    GMS81C5108 2. BLOCK DIAGRAM Common Drive Output COM0 Segment Drive Output COM1/SEG36 COM2/SEG35 SEG0 ~ SEG33 COM3/SEG34 VCL0 VCL1 LCD Display VCL2 LCD Controller/Driver (LCDC) CAPH Voltage Booster CAPL VLCDC Accumulator Stack Pointer Data Memory Program Display Memory Memory Interrupt Controller...

  • Page 7: Pin Assignment

    GMS81C5108 3. PIN ASSIGNMENT RESET VREG R23 / AN3 WDTOUT R22 / AN2 R21 / AN1 R20 / AN0 VCL0 VLCDC SEG0 GMS81C5108 VCL1 VCL2 SEG1 CAPH SEG2 CAPL SEG3 COM0 SEG4 SEG36 / COM1 SEG5 SEG35 / COM2 SEG6...

  • Page 8: Package Diagram

    GMS81C5108 4. PACKAGE DIAGRAM 24.15 23.65 ----------- - UNIT: mm 20.10 19.90 SEE DETAIL "A" 0-7° 1.03 0.73 3.10 max. 1.95 0.8 BSC 0.45 0.30 DETAIL “A” Figure 4-1 Package Diagram JUNE 2001 Ver 1.0 Downloaded from Elcodis.com electronic components distributor...

  • Page 9: Pin Function

    GMS81C5108 5. PIN FUNCTION : Supply voltage. used as outputs or inputs or schmitt trigger inputs. Also, pull- up resistors and open-drain outputs can be assigned by software. : Circuit ground. In addition, R1 serves the functions of the various follow- : Supply voltage to the ladder resistor of ADC cir- ing special features.
  • Page 10 GMS81C5108 Primary Function Secondary Function PIN NAME Pin No. State @ Reset State @ STOP Description Description Supply Voltage Circuit Ground Supply Voltage for Ground for ADC RESET Reset (low active) ‘L’ input ‘H’ input Floating (To be State of before...

  • Page 11: Port Structures

    GMS81C5108 6. PORT STRUCTURES R00~R03/INT0~INT2, R03/EC0, R07/SI R10~R17/KS0~KS7 P u ll up P ull up Pull-up Tr. Pull-up Tr. R e g. R eg . Open Drain Open Drain Reg. Reg. Data Reg. Data Reg. Dir. Reg. Dir. Reg. PMR<0:3,7>...
  • Page 12 GMS81C5108 R30, R32, R33 COM0 VCL2 or VCL1 P u ll up Pull-up Tr. VCL2 R e g. Frame Counter Open Drain Reg. LCD Control Data Reg. VCL1 or V Dir. Reg. COM1/SEG36, COM2/SEG35, COM3/SEG34 M U X VCL2 or VCL1...
  • Page 13 GMS87C5108 (OTP) (RC Option) RESET Internal RESET Noise Canceller Main frequency clock Internal Cap. Mask Option = 5.0pF Default no pull-up GMS81C5108 (MASK) Oscillator RESET Internal RESET Noise STOP Canceller , SX WDTOUT Sub clock WDTOUT WDTOUTEN JUNE 2001 Ver 1.0 Downloaded from Elcodis.com...

  • Page 14: Electrical Characteristics

    GMS81C5108 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Supply voltage ........... -0.3 to +7.0 V Maximum current (ΣI )........60 mA Storage Temperature ........-40 to +125 °C Note: Stresses above those listed under “Absolute Maxi- Voltage on any pin with respect to Ground (V mum Ratings”...

  • Page 15: Dc Electrical Characteristics

    Output Low REMOUT, V =3V, V = 1.0V Leakage Current R0~R3, V Pull-up Resister kΩ RESET, V (GMS81C5108 Mask Option) Main OSC Feedback Resister V Feed Back Resister MΩ Sub OSC Feedback Resister V RC Oscillator R=30kΩ, V Frequency VREG Voltage VREG VREG=0.2uF...

  • Page 16: Lcd Characteristics

    GMS81C5108 7.4 LCD Characteristics (TA=-20~70°C, V =2~4V, V =0V) Specifications Parameter Symbol Condition Unit Min. Typ. Max. ° =3V, TA=25 VLCDC Output Voltage VLCDC R1=1MΩ, R2=300kΩ LCD Reference External Variable Resistance VCL0 Output Voltage (0 to 1MΩ) Double Output Voltage VCL1 C1~C4=0.47uF...

  • Page 17: Ac Characteristics

    GMS81C5108 7.6 AC Characteristics (TA=25°C, V =4V, AV =4V, V =0V) Specifications Parameter Symbol Pins Unit Min. Typ. Max. Main Operating Frequency 0.455 4.19 Sub Operating Frequency 32.768 µS 0.477 4.395 System Clock Frequency Main Oscillation Stabilization Time (4MHz) Main Oscillation...

  • Page 18: Serial I/O Characteristics

    GMS81C5108 7.7 Serial I/O Characteristics (TA=25°C, V =2~4V, V =0V) Specifications Parameter Symbol Pins Unit Min. Typ. Max. +200 SCK Input Clock Pulse Period SCYC SCK Input Clock “H” or “L” Pulse Width SCKW SCK Output Clock Cycle Time SCYC SCK output Clock “H”...

  • Page 19: Typical Characteristics

    GMS81C5108 7.8 Typical Characteristics These graphs and tables are for design guidance only and The data is a statistical summary of data collected on units are not tested or guaranteed. from different lots over a period of time. “Typical” repre- sents the mean of the distribution while “max”...
  • Page 20 GMS81C5108 Operating Area −V MAIN MAIN MAIN (MHz) Ta= -20~70°C Ta=25°C (MHz) (Main-clock) R = 20kΩ R = 47kΩ R = 68kΩ R = 100kΩ Normal Mode (Main opr.) Sleep Mode (Main opr.) Stop Mode −V )−V )−V SLEEP STOP Ta=25°C...

  • Page 21: Memory Organization

    GMS81C5108 8. MEMORY ORGANIZATION The GMS81C5108 has separate address spaces for Pro- to 8K bytes of Program memory. Data memory can be read gram memory, Data Memory and Display memory. Pro- and written to up to 192 bytes including the stack area. Dis- gram memory can only be read, not written to.
  • Page 22 GMS81C5108 [Zero flag Z] or data transfer is “0” and is cleared by any other result. This flag is set when the result of an arithmetic operation RESET VALUE : 00 CARRY FLAG RECEIVES NEGATIVE FLAG CARRY OUT OVERFLOW FLAG...
  • Page 23 GMS81C5108 At execution of a At acceptance At execution At execution CALL/TCALL/PCALL of interrupt of RET instruction of RETI instruction 00BC 00BC 00BC 00BC 00BD 00BD 00BD 00BD Push Push 00BE 00BE 00BE 00BE down down 00BF 00BF 00BF 00BF...

  • Page 24: Program Memory

    GMS81C5108 8.2 Program Memory A 16-bit program counter is capable of addressing up to Example: Usage of TCALL 64K bytes, but this device has 8K bytes program memory space only physically implemented. Accessing a location TCALL 0FH ;1BYTE INSTRUCTION above FFFF will cause a wrap-around to 0000 ;INSTEAD OF 2 BYTES...
  • Page 25 GMS81C5108 Address Program Memory 0FFC0 TCALL 15 TCALL 14 TCALL 13 Address PCALL Area Memory TCALL 12 0FF00 TCALL 11 TCALL 10 TCALL 9 PCALL Area TCALL 8 (256 Bytes) TCALL 7 TCALL 6 TCALL 5 TCALL 4 0FFFF TCALL 3...
  • Page 26 GMS81C5108 Example: The usage software example of Vector address and the initialize part. 0FFE0H NOT_USED NOT_USED NOT_USED NOT_USED WT_INT ; Watch Timer ; Serial I/O AD_Con ; AD converter Carrier_INT ; Carrier INT2 ; Int.2 TMR1_INT ; Timer-1 TMR0_INT ; Timer-0 INT1 ;...

  • Page 27: Data Memory

    The stack provides the area where the return address is User Memory saved before a jump is performed during the processing The GMS81C5108 has 192 × 8 bits for the user memory routine at the execution of a subroutine call instruction or (RAM).
  • Page 28 GMS81C5108 Initial Value Addressing Address Register Name Symbol Page Mode 7 6 5 4 3 2 1 0 00C0 R0 port data register 0 0 0 0 0 0 0 0 byte, bit 00C1 R1 port data register 0 0 0 0 0 0 0 0...
  • Page 29 GMS81C5108 Initial Value Addressing Address Register Name Symbol Page Mode 7 6 5 4 3 2 1 0 00EF Watch timer mode register WTMR - 0 0 0 0 0 0 0 byte, bit 00F0 Key scan mode register KSMR...

  • Page 30: Addressing Mode

    GMS81C5108 8.4 Addressing Mode (3) Direct Page Addressing → → → → dp The GMS81C5108 uses six addressing modes; • Register addressing In this mode, a address is specified within direct page. • Immediate addressing Example; G=0 ;A ←RAM[35 • Direct page addressing C535 •...
  • Page 31 GMS81C5108 X indexed direct page, auto increment→ → → → {X}+ The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR In this mode, a address is specified within direct page by Example; Addressing accesses the address 0135 regard- the X register and the content of X is increased by 1.
  • Page 32 GMS81C5108 Y indexed direct page (8 bit offset) → → → → dp+Y 3F35 This address value is the second byte (Operand) of com- mand plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X.
  • Page 33 GMS81C5108 Y indexed indirect → → → → [dp]+Y Absolute indirect → → → → [!abs] Processes memory data as Data, assigned by the data The program jumps to address specified by 16-bit absolute [dp+1][dp] of 16-bit pair memory paired by Operand in Di- address.

  • Page 34: I/O Ports

    GMS81C5108 9. I/O PORTS The GMS81C5108 has seven ports (R0, R1, R2 and R3), These ports pins may be multiplexed with an alternate and LCD segment port (SEG0~SEG36), and LCD com- function for the peripheral features on the device. mon port (COM0~COM3).

  • Page 35: I/O Ports Configuration

    GMS81C5108 9.2 I/O Ports Configuration R0 Ports R0 is an 8-bit CMOS bidirectional I/O port (address Port Pin Alternate Function ). Each I/O pin can independently used as an input or an output through the R0DR register (address 0C8 INT0 (External Interrupt 0)
  • Page 36 GMS81C5108 R3 Port Port R1 is multiplexed with various special features.The control registers controls the selection of alternate func- R3 is a 4-bit CMOS bidirectional I/O port (address 0C3 tion. After reset, this value is “0”, port may be used as nor- Each I/O pin can independently used as an input or an out- mal I/O port.

  • Page 37: Clock Generator

    GMS81C5108 10. CLOCK GENERATOR As shown in Figure 10-1, the clock generator produces the Instruction cycle time basic clock pulses which provide the system clock to be CPU clock = 4MHz = 32.768kHz supplied to the CPU and the peripheral hardware. It con-...
  • Page 38 GMS81C5108 The system clock is decided by bit1 of the system clock On the initial reset, internal system clock is PS1 which is mode register, SCMR. In selection Sub clock, to oscillate the fastest and other clock can be provided by bit2 and bit3 or stop the Main clock is decided by bit0 of SCMR.

  • Page 39: Operation Mode

    GMS81C5108 10.1 Operation Mode Sub Active mode The system clock controller starts or stops the main-fre- quency clock oscillator and switches between the sub fre- This mode is low-frequency operating mode quency clock. The operating mode is generally divided In this mode, the CPU and the peripheral hardware clock...

  • Page 40: Operation Mode Switching

    Note: In the STOP and SLOW operating modes, the power RESET pin to low, which immediately performs the reset consumption by the oscillator and the internal hardware is operation. After reset, the GMS81C5108 is placed in Main reduced. However, the power for the pin interface (depend- active mode.
  • Page 41 GMS81C5108 Main freq. clock pin) Sub freq. clock pin) Operation clock Main-clock operation Sub-clock operation Changed to the Sub-clock SCMR ← XXXX XX10 Turn off main clock SCMR ← XXXX XX11 (a) Main active mode → → → → Sub active mode Main freq.

  • Page 42: Power Saving Operation

    GMS81C5108 10.3 Power Saving Operation GMS81C5108 has 2 power-saving mode. In power-saving It is released by RESET or interrupt. To be released by in- mode, power consumption is reduced considerably that in terrupt, interrupt should be enabled before Sleep mode.
  • Page 43 GMS81C5108 STOP Mode ing program execution. In Stop mode, the on-chip main- frequency oscillator, system clock, and peripheral clock For applications where power consumption is a critical are stopped (Watch timer clock is oscillating continuous- factor, device provides STOP mode for reducing power ly:.
  • Page 44 GMS81C5108 Example) To release STOP mode, corresponding interrupt should be CKCTLR,#0000_1111B STOP enabled before STOP mode. Specially as a clock source of Timer/Event counter, EC0 pin can release it by Timer/Event counter Interrupt re- quest The Interval Timer Register CKCTLR should be initial-...
  • Page 45 GMS81C5108 Minimizing Current Consumption It should be set properly that current flow through port doesn't exist. The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user First consider the setting to input mode. Be sure that there...

  • Page 46: Basic Interval Timer

    GMS81C5108 11. BASIC INTERVAL TIMER The GMS81C5108 has one 8-bit Basic Interval Timer that interrupt to be generated. The Basic Interval Timer is con- is free-run and can not stop. Block diagram is shown in trolled by the clock control register (CKCTLR) shown in Figure 11-1.
  • Page 47 GMS81C5108 ADDRESS: 0F4 CKCTLR BCK2 BCK1 BCK0 INITIAL VALUE: ----0111 Basic Interval Timer source clock select ÷ ÷ 000: f or f MAIN ÷ ÷ 001: f or f MAIN ÷ ÷ : main-clock frequency 010: f or f MAIN MAIN ÷...

  • Page 48: Timer / Counter

    GMS81C5108 12. Timer / Counter Timer/Event Counter consists of prescaler, multiplexer, 8- ternal clock input. Since a least clock consists of 2 and bit timer data register, 8-bit counter register, mode register, most clock consists of 1024 oscillator periods, the count input capture register and Comparator as shown in Figure rate is 1/2 to 1/1024 of the oscillator frequency in Timer0.
  • Page 49 GMS81C5108 TM0 (Timer0 Mode Register) Bit : ADDRESS: 0E0 CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST INITIAL VALUE:--000000 Reserved CAP0 (Capture Mode Selection Bit) T0CK[2:0] (Timer 0 Input Clock Selection) ÷ ÷ 0: Capture Disable 000: f or f MAIN ÷...
  • Page 50 GMS81C5108 CDR0 (Input Capture Register) T0 (Timer 0 Counter Register) Bit : ADDRESS: E1 CDR07 CDR06 CDR05 CDR04 CDR03 CDR02 CDR01 CDR00 INITIAL VALUE:00H In Timer mode, this register is the value of Timer 0 counter and in Capture mode, this register is the value of input capture.

  • Page 51: 8-Bit Timer/Counter Mode

    1. X: The value “0” or “1” corresponding your operation . Table 12-1 Operating Modes of Timer 0 and Timer 1 12.1 8-Bit Timer/Counter Mode The GMS81C5108 has two 8-bit Timer/Counters, Timer 0, as an 8-bit timer/counter mode, bit CAP0 of TM0 is Timer 1, as shown in Figure 12-3.
  • Page 52 GMS81C5108 These timers have each 8-bit count register and data regis- In counter function, the counter is increased every 0-to 1 ter. The count register is increased by every internal or ex- (rising edge) transition of EC0 pin. In order to use counter ternal clock input.

  • Page 53: Bit Timer/Counter Mode

    GMS81C5108 12.2 16 Bit Timer/Counter Mode The Timer register is running with 16 bits. A 16-bit timer/ The clock source of the Timer 0 is selected either internal counter register T0, T1 are increased from 0000 until it or external clock by bit T0CK2, T0CK1 and T0CK0.
  • Page 54 GMS81C5108 ADDRESS : 0E0H CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST RESET VALUE : --000000 ADDRESS : 0E2H 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST RESET VALUE : 00000000 T0CK[2:0] T0ST 0 : Stop Edge Detector 1 : Clear and Start...
  • Page 55 GMS81C5108 This value is loaded to CDR0 TIME Ext. INT0 Pin Interrupt Request (INT0IF) Interrupt Interval Period Ext. INT0 Pin Interrupt Request (INT0IF) Delay Clear & Start Capture (Timer Stop) Figure 12-8 Input Capture Operation Ext. INT0 Pin Interrupt Request...

  • Page 56: 16-Bit Capture Mode

    Figure 12-10 16-bit Capture Mode 12.5 8-Bit (16-Bit) Compare OutPut Mode The GMS81C5108 has a function of Timer Compare Out- In addition, 16-bit Compare output mode is available, also. put. To pulse out, the timer match can goes to port pin This pin output the signal having a 50 : 50 duty square (R31) as shown in Figure 12-3 and Figure 12-6.
  • Page 57 GMS81C5108 PWM Period = [PWMHR[3:2]T1PPR+1] X Source Clock less PWM output. In Figure 12-11, the duty data is trans- ferred from the master to the slave when the period data PWM Duty = [PWMHR[1:0]T1PDR+1] X Source Clock matched to the counted value. (i.e. at the beginning of next If it needed more higher frequency of PWM, it should be duty cycle).
  • Page 58 GMS81C5108 fxin POL=1 POL=0 Duty Cycle [80 +1 x 250nS = 32.25uS] Period Cycle [3FF x 250nS = 256uS, 3.9kHz] T1CK[1:0] = 00 (250nS) PWM03 PWM02 T1PPR (8-bit) Period PWMHR = 0C T1PPR = FF T1PDR (8-bit) T1PDR = 80...

  • Page 59: Watch Timer/Watch Dog Timer

    GMS81C5108 13. Watch Timer/Watch Dog Timer This has two functions, one is the interrupt occurrence for WDTOUTB for watch dog. watch time and the other is the signal generation of 13.1 Watch Timer The watch timer consists of the clock selector, 21-bit bina- clock source, if the CPU enters into stop mode, the main- ry counter and watch timer mode register.

  • Page 60: Watch Dog Timer

    GMS81C5108 13.2 Watch Dog Timer The watch dog timer (WDT) function is used for checking 1. Determines which mode is to be performed between program malfunction. If the watch dog timer is not reset in main mode and sub mode when the MCU is released a fixed time, the WDTOUTB pin outputs a low signal.

  • Page 61: Analog To Digital Converter

    GMS81C5108 14. ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion setting input mode by R2DR direction register. And select of an analog input signal to a corresponding 8-bit digital the corresponding channel to be converted by setting value. The A/D module has four analog inputs, which are ADAN[1:0].
  • Page 62 GMS81C5108 to noise on pins AV and AN0 to AN3. Since the effect increases in proportion to the output impedance of the an- alog input source, it is recommended that a capacitor is ENABLE A/D CONVERTER connected externally as shown below in order to reduce...

  • Page 63: Buzzer Output Function

    GMS81C5108 15. Buzzer Output Function The buzzer driver consists of 6-bit binary counter, the The bit 0 to 5 of BDR determines output frequency for buzzer data register BDR and the clock selector. It gener- buzzer driving. BCD is undefined after reset, so it must be...
  • Page 64 GMS81C5108 Buzzer Output Frequency When main-frequency is 4MHz, buzzer frequency is source, buzzer frequency is used after dividing by 128. shown as below and if sub-frequency is selected as clock Frequency Output (kHz) Frequency Output (kHz) [5:0] [5:0] 250.000 125.000 62.500...

  • Page 65: Serial Communication Interface

    GMS81C5108 16. Serial Communication Interface The SCI module allows 8-bits of data to be synchronously sists of serial I/O data register, serial I/O mode register, transmitted and received. This is useful for communication clock selection circuit octal counter and control circuit as with other peripheral of microcontroller devices.This con-...

  • Page 66: Data Transmit/Receive Timing

    GMS81C5108 To accomplish communication, typically three pins are ting the SIO1 and SIO0 and the transfer clock rate is decid- used: ed by setting the SICK1 and SICK0 of SCI Mode Control Register as shown in Figure 16-1. And the polarity of...

  • Page 67: The Method Of Serial I/O

    GMS81C5108 16.2 The method of Serial I/O 1. Select transmission/receiving mode If both transmission mode is selected and transmission is per- formed simultaneously it would be made error. When external clock is used, the frequency should be less than 1MHz and recommended duty is 50%.

  • Page 68: Interrupts

    GMS81C5108 17. INTERRUPTS The GMS81C5108 interrupt circuits consist of Interrupt ed by BITIF which is set by overflow of the Basic Interval enable register (IENH, IENL), Interrupt request flag Timer Register (BITR). (IRQH, IRQL), Interrupt Edge Selection Register (IESR), Reset/Interrupt Symbol Priority Vector Addr.

  • Page 69: Interrupt Sequence

    GMS81C5108 The External Interrupts INT0, INT1 and INT2 can each be contains also a master enable bit, I-flag, which disables all transition-activated (1-to-0, 0-to-1 and both transiton).The interrupts at once. When an interrupt is occurred, the I-flag interrupts are controlled by the interrupt master enable flag...
  • Page 70 GMS81C5108 System clock Instruction Fetch SP-2 V.L. V.H. New PC SP-1 Address Bus Not used Data Bus V.L. OP code Internal Read Internal Write Interrupt Processing Step Interrupt Service Routine V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents.

  • Page 71: Brk Interrupt

    GMS81C5108 17.2 BRK Interrupt Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When B-FLAG BRK interrupt is generated, B-flag of PSW is set to distin- guish BRK from TCALL 0.

  • Page 72: External Interrupt

    GMS81C5108 17.4 External Interrupt The external interrupt on INT0, INT1 and INT2 pins are Example: To use as an INT0 and INT2 edge triggered depending on the edge selection register IESR (address 0D8 ) as shown in Figure 17-6. The edge detection of external interrupt has three transition ;**** Set port as an input port R0...

  • Page 73: Key Scan

    GMS81C5108 18. KEY SCAN The key-scan block consists of key scan mode register among R0[7:0], R1[7:0], R2[3:0] and R3[3:0]. (KSMR) and R1 pull-up register (R1PU). When the key If the “L” signal is input to any one or more of key scan in- scan interrupt is used, key scan mode register KSMR (ad- put pins, the KSIF request flag is set to “1”.

  • Page 74: Lcd Driver

    GMS81C5108 19. LCD DRIVER The GMS81C5108 has the circuit that directly drives the The GMS81C5108 has the following pins connected with liquid crystal display (LCD) and its control circuit. The LCD. Segment/Common Driver directly drives the LCD panel, 1. Segment output port 37 pins (SEG0-SEG36) and the LCD Controller generates the segment/common signals according to the RAM which stores display data.

  • Page 75: Control Of Lcd Driver Circuit

    GMS81C5108 19.2 Control of LCD Driver Circuit The LCD driver is controlled by the LCD Control Register Note: The Sub clock is used as voltage booster source (LCR). The LCR[1:0] determines the frequency of COM clock, so the stabilization time is need to use voltage boost- signal scanning of each segment output.

  • Page 76: Lcd Display Memory

    GMS81C5108 19.3 LCD Display Memory Display data are stored to the display data area (page 1) in the data memory. The display data stored to the display data area (address SEG36 0124 0100 -0124 ) are read automatically and sent to the LCD...

  • Page 77: Control Method Of Lcd Driver

    GMS81C5108 19.4 Control Method of LCD Driver Initial Setting Flow chart of initial setting is shown in Figure 19-6. Example: Driving of LCD Select Frame Frequency LCR,#12H =64Hz, 1/4 duty = 32.768kHz) RPR,#1 ;Select LCD Memory(1 page) SETG Clear C_LCD1: LDA ;RAM Clear...
  • Page 78 GMS81C5108 CLRG #<DISPRAM ;Address included the data ;to be displayed. GOLCD: Write into the !FONT+Y ;LOAD FONT DATA RPR,#1 ;Set RPR = 1 to access LCD LCD Memory SETG ;Set Page 1 {X}+ ;LOWER 4 BITS OF ACC. seg0 ;UPPER 4 BITS OF ACC. seg1 CLRG ;Set Page = 0...

  • Page 79: Remocon Carrier Generator

    GMS81C5108 20. REMOCON CARRIER GENERATOR The GMS81C5108 has a circuit to generate carriers for the Data Register (RODR) and Remocon Output Buffer remote controller. This circuit consists of Remocon Mode (ROB) as shown in Figure 20-1. A carrier duty and fre- Register (RMR), Carrier Frequency High Selection (CF- quency are determined by the contents of these registers.

  • Page 80: Carrier Frequency

    GMS81C5108 CFHS (Carrier Frequency High Selection) Bit : ADDRESS : 0F7 CFH5 CFH4 CFH3 CFH2 CFH1 CFH0 RESET VALUE : --111111 Carrier High Interval = The Value of CFHS x Clock Source Period CFLS (Carrier Frequency Low Selection) Bit :...
  • Page 81 GMS81C5108 Carrier Frequency Pulse of Data ROD0 = 01 ROD0 = 00 As soon as the carrier interrupt is occurred, the content of ROB is transferred to RODR. Figure 20-3 Carrier Frequency & Pulse of Data ÷2 The Table 20-1 shows high and low length of carrier fre-...
  • Page 82 GMS81C5108 Example: Carrier Frequency = 37.8kHz, high = 8.52ms, low = 4.24ms, @4MHz Rem_sig: LDM RMR,#0001_0010B ;carrier clock(PS1), remocon data clock(PS5) CFHS,#18 ;carrier low(IR LED)=18*PS1(0.5us)=9us CFLS,#35 ;carrier high(IR LED)=35*PS1(0.5us)=17.5us CLR1 ROD0 R_bit,#1111_1000B RDHR,#213 ;213*5*PS5(8us)=8.52ms RDLR,#177 ;177*3*PS5(8us)=4.248ms CALL DATA SET1 RMR.6 ;Remocon operation enable...

  • Page 83: Oscillator Circuit

    GMS81C5108 21. OSCILLATOR CIRCUIT The GMS81C5108 has two oscillation circuits internally. respectively, inverting amplifier which can be configured and X are input and output for main frequency and for being used as an on-chip oscillator, as shown in Figure and SX are input and output for sub frequency, 21-1.

  • Page 84: Reset

    GMS81C5108 22. RESET The GMS81C5108 have two types of reset generation pro- dog timer reset. Table 22-1 shows on-chip hardware ini- cedures; one is an external reset input, the other is a watch- tialization by reset action. On-chip Hardware Initial Value...

  • Page 85: Supply Voltage Detection

    GMS81C5108 23. SUPPLY VOLTAGE DETECTION The GMS81C5108 has an on-chip low voltage detection not cleared automatically although the V rises above circuitry to detect the V voltage. A configuration regis- 1.7V. It can be cleared by writing. ter, SCMR, can enable or disable the low voltage detect If the SVD1 is set, the MCU can be RESET or frozen by circuitry.

  • Page 86: Devemopment Tools

    5. Start program/verify. mer. Pin Function own programmer list Hynix (Program Voltage) Manufacturer: Hynix Semiconductor Programmer: is the input for the program voltage for programming the Choice-Sigma EPROM. Choice-Gang4 CE (Chip Enable) CE is the input for programming and verifying internal EPROM.

  • Page 87: Emulator S/W Setting

    J_USERB J_USERA SEG46 SEG47 CONNECTA CONNECTB VCL0 SEG44 SEG45 VCL1 VCL2 SEG42 SEG43 VLCDC SEG40 SEG41 SEG38 SEG39 /U_RST VREG SEG37 U_XOUT COM1/S36 COM0 REMOUT (TONED) COM3/S34 COM2/S35 SEG32 SEG33 POWER SEG30 SEG31 SEG28 SEG29 SEG26 SEG27 SEG24 SEG25 SEG22 SEG23 STOP SEG20...
  • Page 88 OFF ON VCL0 0.47uF × 3 Must be ON position. LCD Voltage booster circuit. It is used for the GMS81C5108. Must be OFF position. This switch decide the Stack page 0 Select the Stack Page. (off) or page 1 (on).
  • Page 89 GMS81C5108 DIP S/W, VR Description ON/OFF Setting Internal power supply to sub-oscillation circuit. Must be ON position. Reserved for other purpose. Must be OFF position. OFF ON Adjust the LCD contrast. It control the VCL2 voltage. Adjust the proper position as well as Refer to above SW4-1,2,3 figure.
  • Page 90 GMS81C5108 Book History This Book Ver 1.0 (JUNE 2001) First edition. JUNE 2001 Ver 1.0 Downloaded from Elcodis.com electronic components distributor...
  • Page 91 APPENDIX Downloaded from Elcodis.com electronic components distributor...
  • Page 92 GMS81C5108 APPENDIX A. CONTROL REGISTER LIST Initial Value Address Register Name Symbol Page 7 6 5 4 3 2 1 0 00C0 R0 port data register 0 0 0 0 0 0 0 0 00C1 R1 port data register 0 0 0 0 0 0 0 0...
  • Page 93 GMS81C5108 APPENDIX Initial Value Address Register Name Symbol Page 7 6 5 4 3 2 1 0 00EF Watch timer mode register WTMR - 0 0 0 0 0 0 0 00F0 Key scan mode register KSMR 0 0 0 0 0 0 0 0...
  • Page 94 GMS81C5108 APPENDIX B. INSTRUCTION B.1 Terminology List Terminology Description Accumulator X - register Y - register Program Status Word #imm 8-bit Immediate data Direct Page Offset Address !abs Absolute Address Indirect expression Register Indirect expression { }+ Register Indirect expression, after that, Register auto-increment .bit...

  • Page 95: Instruction Map

    GMS81C5108 APPENDIX B.2 Instruction Map 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 HIGH SET1 TCALL SETA1 PUSH dp.bit A.bit,rel dp.bit,rel #imm dp+X !abs .bit TCALL CLRA1 PUSH CLRC #imm dp+X !abs .bit...

  • Page 96: Instruction Set

    GMS81C5108 APPENDIX B.3 Instruction Set Arithmetic / Logic Operation Byte Cycle Flag Mnemonic Operation Code NVGBHIZC ADC #imm Add with carry. A ← ( A ) + ( M ) + C ADC dp ADC dp + X ADC !abs...
  • Page 97 GMS81C5108 APPENDIX Byte Cycle Flag Mnemonic Operation Code NVGBHIZC Divide : YA / X Q: A, R: Y NV--H-Z- EOR #imm Exclusive OR A ← ( A ) ⊕ ( M ) EOR dp EOR dp + X EOR !abs...
  • Page 98 GMS81C5108 APPENDIX Register / Memory Operation Byte Cycle Flag Mnemonic Operation Code NVGBHIZC LDA #imm Load accumulator A ← ( M ) LDA dp LDA dp + X LDA !abs LDA !abs + Y N-----Z- LDA [ dp + X ]...
  • Page 99 GMS81C5108 APPENDIX 16-BIT operation Byte Cycle Flag Mnemonic Operation Code NVGBHIZC 16-Bits add without Carry ADDW dp NV--H-ZC YA ← ( YA ) + ( dp +1 ) ( dp ) Compare YA contents with memory pair contents : CMPW dp N-----ZC (YA) −...
  • Page 100 GMS81C5108 APPENDIX Branch / Jump Operation Byte Cycle Flag Mnemonic Operation Code NVGBHIZC BBC A.bit,rel Branch if bit clear : -------- if ( bit ) = 0 , then pc ← ( pc ) + rel BBC dp.bit,rel BBS A.bit,rel...
  • Page 101 GMS81C5108 APPENDIX Control Operation & Etc. Byte Cycle Flag Mnemonic Operation Code NVGBHIZC Software interrupt : B ← ”1”, M(sp) ← (pc ), sp ←sp-1, M(s) ← (pc ), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, ---1-0-- ←...

  • Page 102: Mask Order Sheet

    C. MASK ORDER SHEET MASK ORDER & VERIFICATION SHEET GMS81C5108 - UD Customer should write inside thick line box. 1. Customer Information 2. Device Information Package 80QFP Company Name ROM Size Application OSC Option Crystal YYYY Reset Pull Up Order Date...

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