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Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
GMS81508B/16B/24B, GMS82512/16/24 Table of Contents 1. OVERVIEW ...........1 The Serial I/O operation by SRDY pin .... 53 The method of Serial I/O ......... 54 Description ............1 The Method to Test Correct Transmission ..54 Features .............1 14. PWM OUTPUT .........55 Development Tools ..........2 15.
GMS81508B/16B/24B, GMS82512/16/24 GMS81508B/16B/24B GMS82512/16/24 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH A/D CONVERTER 1. OVERVIEW 1.1 Description The GMS81508B/16B/24B are advanced CMOS 8-bit microcontrollers with 8K/16K/24K bytes of ROM and 64pin package. And the GMS82512/16/24 are the same except for 12K/16K/24K bytes of ROM and 42pin package. The GMS825xx is a cut-down product of GMS815xxB microcontroller, that is, the function and package are reduced.
For more detail, Refer to “22. OTP PROGRAMMING” on page 76. Macro assembler operates under the MS-Windows 95/98 Please contact sales part of Hynix Semiconductor. 1.4 Ordering Information Device name ROM Size...
GMS81508B/16B/24B, GMS82512/16/24 5. PIN FUNCTION R50~R53, R56, R57 are NOT served on GMS825xx. : Supply voltage. : Circuit ground. In addition, R5 serves the functions of the various follow- ing special features. TEST: Used for Test Mode. For normal operation, it should be connected to V Port pin Alternate function...
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GMS81508B/16B/24B, GMS82512/16/24 Function PIN NAME In/Out Basic Alternate Supply voltage Circuit ground Controls test mode of the chip, TEST For normal operation, it should be connected at V RESET Reset signal input Oscillation input Oscillation output R00~R07 8-bit general I/O ports 8-bit general I/O ports R10~R17 R20~R27...
GMS81508B/16B/24B, GMS82512/16/24 6. PORT STRUCTURES R00~R07, R10~R17, R20~R27, R30~37 R52/SCLK Selection Data Reg. SCK Output M U X Dir. Reg. Data Reg. Direction M UX Reg. M U X exck M U X R40/INT0, R41/INT1, R42/INT2, R43/INT3, R44/ EC0, R45/EC2, R50/SIN SCK Input PMR Selection Data Reg.
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GMS81508B/16B/24B, GMS82512/16/24 R60/AN0 ~ R63/AN3 RESET RESET Data bus To A/D converter R64/AN7 ~ R67/AN7 TEST OTP version: disconnected Mask version: connected Data Reg. TEST Dir. Reg. M U X To A/D converter XOUT Stop MAY. 2001 Ver 2.0 http://www.xinpian.net 提供单片机解密、IC解密、芯片解密业务...
GMS81508B/16B/24B, GMS82512/16/24 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Supply voltage ..........-0.3 to +7.0 V Maximum current (ΣI ) ........100 mA Storage Temperature ........-40 to +125 °C Maximum current (ΣI )........50 mA Voltage on any pin with respect to Ground (V Note: Stresses above those listed under “Absolute Maxi- ..............-0.3 to V +0.3...
GMS81508B/16B/24B, GMS82512/16/24 Specifications Max. Parameter Symbol Unit Min. Typ. =4MHz =8MHz 0.9V 1.1V Analog Power Supply Input Range 1. Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 7.4 DC Electrical Characteristics =-20~85°C, V =2.7~5.5V, Ta= -20~85°C, f...
GMS81508B/16B/24B, GMS82512/16/24 7.6 Serial Interface Timing Characteristics =-20~+85°C, V =5V±10%, V =0V, f =8MHz) Specifications Parameter Symbol Pins Unit Min. Typ. Max. +200 Serial Input Clock Pulse SCLK SCYC Serial Input Clock Pulse Width SCLK SCKW Serial Input Clock Pulse Transition FSCK SCLK Time...
GMS81508B/16B/24B, GMS82512/16/24 7.7 Typical Characteristic Curves This graphs and tables provided in this section are for de- The data presented in this section is a statistical summary sign guidance only and are not tested or guaranteed. of data collected on units from different lots over a period of time.
GMS81508B/16B/24B, GMS82512/16/24 8. MEMORY ORGANIZATION The GMS81508B/16B/24B and GMS82512/16/24 have to. It can be up to 24K bytes of Program memory. Data separate address spaces for Program memory and Data memory can be read and written to up to 448 bytes includ- Memory.
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GMS81508B/16B/24B, GMS82512/16/24 [Zero flag Z] or data transfer is “0” and is cleared by any other result. This flag is set when the result of an arithmetic operation V G B H RESET VALUE: 00 CARRY FLAG RECEIVES NEGATIVE FLAG CARRY OUT OVERFLOW FLAG ZERO FLAG...
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GMS81508B/16B/24B, GMS82512/16/24 At execution of At acceptance At execution At execution a CALL/TCALL/PCALL of interrupt of RET instruction of RET instruction Push 01FE 01FE 01FE 01FE down Push 01FD 01FD 01FD 01FD down 01FC 01FC 01FC 01FC 01FB 01FB 01FB 01FB SP before 01FE...
GMS81508B/16B/24B, GMS82512/16/24 8.2 Program Memory A 16-bit program counter is capable of addressing up to it is more useful to save program byte length. 64K bytes, but this device has 24K bytes program memory Table Call (TCALL) causes the CPU to jump to each space only physically implemented.
GMS81508B/16B/24B, GMS82512/16/24 8.3 Data Memory Figure 8-8 shows the internal Data Memory space availa- Note that unoccupied addresses may not be implemented ble. Data Memory is divided into four groups, a user RAM, on the chip. Read accesses to these addresses will in gen- control registers, Stack, and LCD memory.
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GMS81508B/16B/24B, GMS82512/16/24 Initial Value Address Register Name Symbol Page 7 6 5 4 3 2 1 0 00C0 R0 port data register Undefined page 34 00C1 R0 port I/O direction register R0DD 0 0 0 0 0 0 0 0 page 34 R1 port data register Undefined...
GMS81508B/16B/24B, GMS82512/16/24 8.4 Addressing Mode The GMS800 series MCU uses six addressing modes; Example: G=1 • Register addressing E45535 35H,#55H • Immediate addressing • Direct page addressing • Absolute addressing 0135H data data ¨ 55H • Indexed addressing • Register-indirect addressing þ...
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GMS81508B/16B/24B, GMS82512/16/24 (4) Absolute Addressing → → → → !abs ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Absolute addressing sets corresponding memory data to Example; X=15 , G=1 Data, i.e. second byte (Operand I) of command becomes ;ACC←RAM[X]. lower level address and third byte (Operand II) becomes upper level address.
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GMS81508B/16B/24B, GMS82512/16/24 Example; G=0 C645 45H+X 3F35 [35H] data à À À → data þ 0E550H þ 0E30AH NEXT jump to 0E551H address 0E30AH 45H+0F5H=13AH 0FA00H Y indexed direct page (8 bit offset) → → → → dp+Y This address value is the second byte (Operand) of com- X indexed indirect →...
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GMS81508B/16B/24B, GMS82512/16/24 Example; G=0 1725 [25H]+Y 1F25E0 [!0C025H] PROGRAM MEMORY À þ 0E025H 0E005H + Y(10) 0E015H data = 0E015H 0E026H À jump to address 0E30AH 0FA00H 0E725H NEXT þ Ã → A + data + C 0FA00H Absolute indirect → → → → [!abs] The program jumps to address specified by 16-bit absolute address.
GMS81508B/16B/24B, GMS82512/16/24 9. I/O PORTS The GMS815xxB and GMS825xx have four input ports R1 and R1DD register: R1 is an 8-bit CMOS bidirection- and fifty two input/output ports(R00~R67) and the al I/O port (address 0C2 ). Each I/O pin can independently GMS825xx has thirty five input/output ports.
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GMS81508B/16B/24B, GMS82512/16/24 R3 and R3DD register: R3 is an 8-bit CMOS bidirection- al I/O port (address 0C6 ). Each I/O pin can independently Regardless of the direction register R4DD, PMR4 is select- used as an input or an output through the R3DD register ed to use as alternate functions, port pin can be used as a (address 0C7 corresponding alternate features.
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GMS81508B/16B/24B, GMS82512/16/24 R5 and R5DD register: R5 is an 8-bit CMOS bidirection- al I/O port (address 0CA ). Each I/O pin can independent- R6 and R6DD register: R6 is an 8-bit CMOS bidirection- ly used as an input or an output through the R5DD register al I/O port (address 0CC ).
GMS81508B/16B/24B, GMS82512/16/24 10. BASIC INTERVAL TIMER The GMS815xxB and GMS825xx have one 8-bit Basic In- generated. The Basic Interval Timer is controlled by the terval Timer that is free-run and can not stop. Block dia- clock control register (CKCTLR) shown in Figure 10-2. gram is shown in Figure 10-1.
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GMS81508B/16B/24B, GMS82512/16/24 ADDRESS: 0D3 CKCTLR BTCL BTCL BTS2 BTS1 BTS0 WDTON ENPCK INITIAL VALUE: --01 0111 Basic Interval Timer source clock select ÷ 000: f ÷ 001: f ÷ 010: f ÷ 011: f ÷ 100: f ÷ 101: f ÷...
GMS81508B/16B/24B, GMS82512/16/24 11. TIMER/EVENT COUNTER The GMS815xxB and GMS825xx have four Timer/ (EC2 are NOT served on GMS825xx.) Counter registers. Each module can generate an interrupt In addition the “capture” function, the register is incre- to indicate that an event has occurred (i.e. timer match). mented in response external or internal clock sources same Timer 0 and Timer 1 are can be used either two 8-bit Tim- with timer or counter function.
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GMS81508B/16B/24B, GMS82512/16/24 A D D R E S S : 0E 2 C A P 0 T1S T T1S L1 T1S L0 B TC L T0S T T0C N T0S L1 T0S L0 IN ITIA L V A LU E : 00 Bit Name Bit Position Description...
GMS81508B/16B/24B, GMS82512/16/24 11.1 8-bit Timer / Counter Mode The GMS815xxB and GMS825xx have four 8-bit Timer/ T3SL1, T3SL0 of TM2 should not set to zero. These timers Counters, Timer 0, Timer 1, Timer 2, Timer 3. The Timer have each 8-bit count register and data register. The count 0, Timer 1 are shown in Figure .
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GMS81508B/16B/24B, GMS82512/16/24 In counter function, the counter is increased every 1-to-0 Note: The contents of Timer data register TDRx should be (falling edge) transition of EC0 or EC2 pin. In order to use initialized 1 , not 0 , because it is undefined after re- counter function, the bit 4, bit 5 of the Port mode register set.
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GMS81508B/16B/24B, GMS82512/16/24 8-bit Timer Mode Maximum Time Resolution Value of Clock Setting In the timer mode, the internal clock is used for counting (At f =8 M H z) TM[1:0] Source (At f =8 M H z) up. Thus, you can think of it as counting internal clock in- ×...
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GMS81508B/16B/24B, GMS82512/16/24 8-bit Event Counter Mode In order to use event counter function, the bit 4, 5 of the Port Mode Register PMR4(address 0D0 ) is required to be In this mode, counting up is started by an external trigger. set to “1”.
GMS81508B/16B/24B, GMS82512/16/24 11.2 16-bit Timer / Counter Mode The Timer register is being run with all 16 bits. A 16-bit Even if the Timer 0 (including the Timer 1) is used as a 16- timer/counter register T0, T1 are incremented from 0000 bit timer, the Timer 2 and Timer 3 can still be used as either until it matches TDR0, TDR1 and then resets to 0000 two 8-bit timer or one 16-bit timer by setting the TM2.
GMS81508B/16B/24B, GMS82512/16/24 11.3 8-bit Capture Mode The Timer 0 capture mode is set by bit CAP0 of timer causes the current value in the Timer counter register mode register TM0 (bit CAP2 of timer mode register TM2 (T0,T2), to be captured into registers CDRn (CDR0, for Timer 2) as shown in Figure 21.
GMS81508B/16B/24B, GMS82512/16/24 11.4 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. ADDRESS: 0E2 CAP0 T1ST T1SL1 T1SL0 BTCL T0ST T0CN T0SL1 T0SL0 INITIAL VALUE: 00 X means don’t care T0SL[1:0] Edge Detector...
GMS81508B/16B/24B, GMS82512/16/24 12. ANALOG DIGITAL CONVERTER R60 ~ R63 are NOT served on GMS825xx. The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital How to Use A/D Converter value. The A/D module has eight analog inputs, which are multiplexed into one sample and hold.
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GMS81508B/16B/24B, GMS82512/16/24 ADDRESS: 0E8 ADCM BTCL ADEN ADS2 ADS1 ADS0 ADST ADSF INITIAL VALUE: --00 0001 A/D status bit 0: A/D conversion is in progress 1: A/D conversion is completed A/D start bit Setting this bit starts an A/D conversion. After one cycle, bit is cleared to “0”...
GMS81508B/16B/24B, GMS82512/16/24 13. SERIAL COMMUNICATION - This function is NOT served on the GMS825xx. The serial iterface is used to transmit/receive 8-bit data se- trolled by the Serial Mode Register. The contents of the Se- rially. This consists of serial I/O data register, serial I/O rial I/O data register can be written into or read out by mode register, clock selection circuit octal counter and software.
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GMS81508B/16B/24B, GMS82512/16/24 Serial I/O Mode Register(SIOM) controls serial I/O func- Serial I/O Data Register(SIOR) is an 8-bit shift register. tion. According to SCK1 and SCK0, the internal clock or First LSB is send or is received. external clock can be selected. ADDRESS: 0EA SIOM BTCL...
GMS81508B/16B/24B, GMS82512/16/24 13.1 Transmission/Receiving Timing The serial transmission is started by setting SIOST(bit1 of is latched at rising edge of SCLK pin. When transmission SIOM) to “1”. After one cycle of SCK, SIOST is cleared clock is counted 8 times, serial I/O counter is cleared as automatically to “0”.
GMS81508B/16B/24B, GMS82512/16/24 13.3 The method of Serial I/O 1. Select transmission/receiving mode. Note: When external clock is used, the frequency should 2. In case of sending mode, write data to be send to SIOR. be less than 1MHz and recommended duty is 50%. If both transmission mode is selected and transmission is per- 3.
GMS81508B/16B/24B, GMS82512/16/24 14. PWM OUTPUT - This function is NOT served on the GMS825xx. The GMS815xxB have two channels of built-in pulse The input clock is selected by PWM Control Register width modulation outputs. PWM outputs data are multi- (PWMCR, address F2 ) and the width of pulse is deter- plex to the R56 and R57 port.
GMS81508B/16B/24B, GMS82512/16/24 15. BUZZER FUNCTION The buzzer driver block consists of 6-bit binary counter, The bit 0 to 5 of BUR determines output frequency for buzzer register, and clock source selector. It generates buzzer driving. square-wave which has very wide range frequency (500Hz Equation of frequency calculation is shown below.
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GMS81508B/16B/24B, GMS82512/16/24 The 6-bit counter is cleared and starts the counting by writ- Note: BUR is undefined after reset, so it must be initialized ing signal at BUR register. It is incremental from 00 until to between 1 and 3F by software.
GMS81508B/16B/24B, GMS82512/16/24 16. INTERRUPTS IRQH and IRQL) except Power-on reset and software The GMS815xxB and GMS825xx interrupt circuits con- sist of Interrupt enable register (IENH, IENL), Interrupt re- BRK interrupt. Below table shows the Interrupt priority. quest flags of IRQH, IRQL, Priority circuit, and Master enable flag (“I”...
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GMS81508B/16B/24B, GMS82512/16/24 Internal bus line [0F6 I-flag is in PSW, it is cleared by “DI”, set by Interrupt Enable “EI” instruction. When it goes interrupt service, IENH I-flag is cleared by hardware, thus any other Register (Higher byte) IRQH interrupt are inhibited. When interrupt service is completed by “RETI”...
GMS81508B/16B/24B, GMS82512/16/24 16.1 Interrupt Sequence An interrupt request is held until the interrupt is accepted 2. Interrupt request flag for the interrupt source accepted is or the interrupt latch is cleared to “0” by a reset or an in- cleared to “0”. struction.
GMS81508B/16B/24B, GMS82512/16/24 16.2 BRK Interrupt area for saving registers. Software interrupt can be invoked by BRK instruction, The following method is used to save/restore the general- which has the lowest priority order. purpose registers. Interrupt vector address of BRK is shared with the vector Example: Register save using push and pop instructions of TCALL 0 (Refer to Program Memory Section).
GMS81508B/16B/24B, GMS82512/16/24 16.3 Multi Interrupt If two requests of different priority levels are received si- However, multiple processing through software for special multaneously, the request of higher priority level is ser- features is possible. Generally when an interrupt is accept- viced.
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GMS81508B/16B/24B, GMS82512/16/24 activated mode: rising edge, falling edge, and both edge. spondingly. Example: To use as an INT0 and INT2 INT0 pin INT0IF ;**** Set port as an input port R40,R42 INT0 INTERRUPT R4DD,#1111_1010B ;**** Set port as an external interrupt port INT1 pin INT1IF PMR4,#05H...
GMS81508B/16B/24B, GMS82512/16/24 17. WATCHDOG TIMER When the watchdog timer is not being used for malfunc- The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and re- tion detection, it can be used as a timer to generate an in- sumes the CPU to the normal state.
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GMS81508B/16B/24B, GMS82512/16/24 Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz ;Select 1/2048 clock source, WDTON ← 1, Clear Counter CKCTLR,#3FH WDTR,#04FH ;Clear counter WDTR,#04FH Within WDT detection time ;Clear counter WDTR,#04FH Within WDT detection time ;Clear counter WDTR,#04FH Enable and Disable Watchdog Watchdog Timer Interrupt...
GMS81508B/16B/24B, GMS82512/16/24 18. POWER DOWN OPERATION GMS815xxB has a power-down mode. In power-down STOP Mode is entered by STOP instruction. mode, power consumption is reduced considerably that in battery operation. Battery life can be extended a lot. 18.1 STOP Mode For applications where power consumption is a critical Note: Since the X pin is connected internally to GND to...
GMS81508B/16B/24B, GMS82512/16/24 Release the STOP mode the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. The exit from STOP mode is using hardware reset or exter- nal interrupt. Start-up is performed to acquire the time for stabilizing os- cillation.
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GMS81508B/16B/24B, GMS82512/16/24 is external pull-down register, it is set to low. INPUT PIN INPUT PIN internal pull-up OPEN Very weak current flows OPEN Weak pull-up current flows When port is configure as an input, input level should be closed to 0V or 5V to avoid power consumption. Figure 18-2 Application Example of Unused Input Port OUTPUT PIN OUTPUT PIN...
GMS81508B/16B/24B, GMS82512/16/24 19. OSCILLATOR CIRCUIT The GMS815xxB has two oscillation circuits internally. tively, inverting amplifier which can be configured for be- and X are input and output for frequency, respec- ing used as an on-chip oscillator, as shown in Figure 19-1. Open 8MHz External Clock...
GMS81508B/16B/24B, GMS82512/16/24 20. RESET The GMS815xxB have two types of reset generation pro- dog timer reset. Table 20-1 shows on-chip hardware ini- cedures; one is an external reset input, the other is a watch- tialization by reset action. On-chip Hardware Initial Value On-chip Hardware Initial Value...
GMS81508B/16B/24B, GMS82512/16/24 21. POWER FAIL PROCESSOR The GMS815xxB and GMS825xx have an on-chip power Note: If power fail voltage is selected to 3.0V on 3V oper- fail detection circuitry to immunize against power noise. A ation, MCU is freezed at all the times. configuration register, PFDR, can enable or disable the power fail detect circuitry.
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GMS81508B/16B/24B, GMS82512/16/24 RESET VECTOR PFS =1 RAM CLEAR INITIALIZE RAM DATA PFS = 0 Skip the INITIALIZE ALL PORTS initial routine INITIALIZE REGISTERS FUNTION EXECUTION Figure 21-2 Example S/W of RESET flow by Power fail 64mS Internal RESET When PFR = 1 64mS Internal t <64mS...
A000H grammer or third party universal programmer shown as listed below. 4. Mount the socket adapter on the programmer. 5. Start program/verify. Hynix own programmer list Hynix Semiconductor Inc. Manufacturer: 22.2 Pin Function Programmer: Choice-Sigma, Stand-alone Gang4 (Program Voltage) is the input for the program voltage for programming Choice-Sigma is a Hynix universal single programmer for the EPROM.
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GMS81508B/16B/24B, GMS82512/16/24 64SDIP OPEN 64MQFP GMS815016BT/24BT OPEN Table 22-1 Socket Adapter Pin Assignment for GMS81516BT/24BT MAY. 2001 Ver 2.0 http://www.xinpian.net 提供单片机解密、IC解密、芯片解密业务 010-62245566 13810019655...
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GMS81508B/16B/24B, GMS82512/16/24 64LQFP GMS81516BT/24BT OPEN Table 22-2 Socket Adapter Pin Assignment for GMS81516BT/24BT MAY. 2001 Ver 2.0 http://www.xinpian.net 提供单片机解密、IC解密、芯片解密业务 010-62245566 13810019655...
GMS81508B/16B/24B, GMS82512/16/24 22.3 Programming Specification DEVICE OPERATION MODE = 25°C ± 5°C) Mode A0~A15 O0~O7 Read Mode 5.0V DOUT Output Disable Mode 5.0V Hi-Z Programming Mode Program Verify DOUT 1. X = Either V or V 2. See DC Characteristics Table for V and V voltage during programming.
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GMS81508B/16B/24B, GMS82512/16/24 SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change Will be changing from H to L from H to L May change Will be changing from L to H from L to H Do not care any Changing state change permitted unknown...
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GMS81508B/16B/24B, GMS82512/16/24 PROGRAMMING ALGORITHM WAVEFORMS Program Program Verify Addresses Addresses Valid High-Z Data In/Out Data out valid Data in Stable 12.75V 6.25V 5.0V 1. The input timing reference level is 1.0V for a V and 4.0V for a V at V =5.0V.
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GMS81508B/16B/24B, GMS82512/16/24 AC READING CHARACTERISTICS =0V, T = 25°C ± 5°C) Symbol Item Unit Test condition µs Address setup time Quick Pulse Programming supply current Note: V must be applied simultaneously or before V and removed simultaneously or after V AC PROGRAMMING CHARACTERISTICS =0V, T = 25°C ±...
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GMS81508B/16B/24B, GMS82512/16/24 START ADDRESS=FIRST LOCATION =6.0V =11.75 PROGRAM ONE 100µs PULSE INCREMENT X X=25? FAIL VERIFY FAIL VERIFY BYTE ONE BYTE PASS PASS LAST INCREMENT ADDRESS? ADDRESS =5.0V COMPARE FAIL ALL BYTES TO ORIGINAL DATA PASS DEVICE DEVICE PASSED FAILED Table 22-4 Programming Algorithm MAY.
GMS81508B/16B/24B, GMS82512/16/24 A. CONTROL REGISTER LIST Initial Value Address Register Name Symbol Page 7 6 5 4 3 2 1 0 00C0 R0 port data register Undefined 00C1 R0 port I/O direction register R0DD 0 0 0 0 0 0 0 0 R1 port data register Undefined 00C2...
GMS81508B/16B/24B, GMS82512/16/24 C. INSTRUCTION C.1 Terminology List Terminology Description A - Register X - Register Y - Register Program Status Word Carry Flag of PSW Overflow Flag of PSW Negative Flag of PSW Master Interrupt Enable Flag of PSW Zero Flag of PSW Half Carry Flag of PSW Break Flag of PSW (software interrupt) G flag of PSW(Direct Page)
GMS81508B/16B/24B, GMS82512/16/24 C.3 Alphabetic order table of instruction BYTE CYCLE FLAG MNENONIC OPERATION CODE NVGBHIZC ADC #imm Add with carry. A ← A + (M) + C ADC dp ADC dp + X ADC !abs NV - - H - ZC ADC !abs+Y ADC [dp+X] ADC [dp]+Y...
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GMS81508B/16B/24B, GMS82512/16/24 BYTE CYCLE FLAG MNENONIC OPERATION CODE NVGBHIZC CBNE dp,rel Compare and branch if not equal ; - - - - - - - - CBNE dp + X, If A ≠ (M), then PC ← PC + rel. Clear bit : (M.bit) ←...
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GMS81508B/16B/24B, GMS82512/16/24 BYTE CYCLE FLAG MNENONIC OPERATION CODE NVGBHIZC (M) ← (M) + 1 INC dp INC dp + X INC !abs N - - - - - Z - INC X INC Y Increment memory pair : (dp+1)(dp) ← {(dp+1)(dp)} + 1 INCW dp N - - - - - Z - JMP !abs...
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GMS81508B/16B/24B, GMS82512/16/24 BYTE CYCLE FLAG MNENONIC OPERATION CODE NVGBHIZC 138 POP A Pop from stack SP ← SP + 1, Reg. ← M(SP) 139 POP X - - - - - - - - 140 POP Y 141 POP PSW (restored) 142 PUSH A Push to stack...
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GMS81508B/16B/24B, GMS82512/16/24 BYTE CYCLE FLAG MNENONIC OPERATION CODE NVGBHIZC Transfer accumulator contents to X-register : X ← A 186 TAX N - - - - - Z - Transfer accumulator contents to Y-register : Y ← A 187 TAY N - - - - - Z - 188 TCALL n Table call : ), SP ←...
D. MASK ORDER SHEET MASK ORDER & VERIFICATION SHEET GMS81508B GMS81516B GMS81524B Customer should write inside thick line box. 1. Customer Information 2. Device Information Company Name Package 64SDIP 64MQFP 64LQFP Internet Hitel Chollian Application File Name ) .OTP YYYY Order Date ROM Size (bytes) Tel:...
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MASK ORDER & VERIFICATION SHEET GMS82512 GMS82516 GMS82524 Customer should write inside thick line box. 1. Customer Information 2. Device Information Company Name Package 42SDIP 44MQFP Internet Hitel Chollian Application File Name ) .OTP YYYY Order Date ROM Size (bytes) Tel: Fax: Check Sum...
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