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NXP Semiconductors AN13125 Application Note

NXP Semiconductors AN13125 Application Note

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AN13125
IW416 Design Guide
Rev. 1 — 26 May 2021
Document information
Information
Content
Keywords
Power supply, clock source, reset, host interface, RF interface, PCB layout,
PCB stackup
Abstract
Provides design guidelines for IW416 device.
Application note

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Summary of Contents for NXP Semiconductors AN13125

  • Page 1 AN13125 IW416 Design Guide Rev. 1 — 26 May 2021 Application note Document information Information Content Keywords Power supply, clock source, reset, host interface, RF interface, PCB layout, PCB stackup Abstract Provides design guidelines for IW416 device.
  • Page 2 AN13125 NXP Semiconductors IW416 Design Guide Revision history Date Description 20210526 Initial version AN13125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Application note Rev. 1 — 26 May 2021...

  • Page 3: Overview

    AN13125 NXP Semiconductors IW416 Design Guide Overview This document provides design guidelines for NXP IW416 device. The IW416 is a highly integrated Wi-Fi 4 (2.4 GHz/5 GHz) and Bluetooth 5.1 single-chip solution. ® ® The IW416 is available in two package options – QFN and WLCSP.

  • Page 4: Power Supply

    AN13125 NXP Semiconductors IW416 Design Guide Power supply 2.1 Power supply overview Table 1 lists the power supplies. Table 1. Power supplies Supply Description Typical value VCORE Core power supply 1.05 V AVDD18 Analog power supply 1.8 V Wi-Fi PA power supply 2.2 V Digital I/O power supply 1.8 V or 3.3 V...

  • Page 5: Power Supply Using Mps Pmics

    AN13125 NXP Semiconductors IW416 Design Guide 2.2 Power supply using MPS PMICs Figure 1 shows a simplified block diagram using the MPS MP2182, MP2162A and MP8904. Two control signals, DVSC1 and DVSC0, are used to control the core voltage level.

  • Page 6: Power Supply Using Nxp Pm823 Or Marvell 88Pg823

    AN13125 NXP Semiconductors IW416 Design Guide 2.3 Power supply using NXP PM823 or Marvell 88PG823 Figure 2 shows a simplified block diagram using the NXP PM823 or Marvell 88PG823 (QFN). Two control signals, DVSC1 and DVSC0, are used to control the core voltage level.

  • Page 7: Pcb Layout Guidelines

    AN13125 NXP Semiconductors IW416 Design Guide 2.5 PCB layout guidelines Refer to the following PCB layout guidelines for power supply. • Follow the PMIC schematic/layout exactly. Any deviation must be reviewed with PMIC vendor Applications Engineer. • Use power planes (layer) and polygons to lower the power impedance.
  • Page 8 AN13125 NXP Semiconductors IW416 Design Guide • There is a decoupling capacitor for each power pin and a bulk capacitor for each rail. Place the decoupling capacitor as close as possible to the power pin, then place the bulk capacitor.

  • Page 9: Clock Source

    AN13125 NXP Semiconductors IW416 Design Guide Clock source Two main clock sources are available: a crystal, and an external oscillator. An optional sleep clock is also available for low power mode. 3.1 Crystal In a typical application, a 26 MHz or 40 MHz crystal is used as a reference clock source.
  • Page 10 AN13125 NXP Semiconductors IW416 Design Guide • Keep XTAL_IN and XTAL_OUT traces as short as possible, as shown in Figure Figure 8. Crystal PCB layout • Make sure XTAL_IN and XTAL_OUT traces are referenced to the solid ground plane in the second layer.

  • Page 11: External Oscillator

    AN13125 NXP Semiconductors IW416 Design Guide 3.2 External oscillator Figure 9 shows the typical application circuit for an external oscillator. Figure 9. External oscillator circuit An external 26 MHz external oscillator may be used as reference clock source. If using an external oscillator, make sure its frequency accuracy meets the ±20 ppm IEEE specification over the operating temperature range of the product.

  • Page 12: Reset

    AN13125 NXP Semiconductors IW416 Design Guide Reset 4.1 Reset overview Power on reset (POR) is triggered when the correct power up sequence is followed. Refer to IW416 data sheet for details on power up sequence requirements. The PDn signal is used to reset the Wireless SoC. On the NXP reference design, the PDn signal is pulled up to VIO to meet the power-up sequence requirements.

  • Page 13: Host Interface

    AN13125 NXP Semiconductors IW416 Design Guide Host interface Table 4 lists the supported host interfaces. Table 4. Wi-Fi and Bluetooth host interfaces Wi-Fi Bluetooth SDIO 3.0 UART 5.1 SDIO interface The SDIO interface has the following characteristics: • SDIO v3.0 is backward compatible with SDIO v2.0 HOST. SDIO 3.0 is recommended for maximum throughput.
  • Page 14 AN13125 NXP Semiconductors IW416 Design Guide PCB layout guidelines for SDIO interface Refer to the following PCB layout guidelines for SDIO interface: • SDIO signals are routed with 50(±10%) ohm impedance • Route the SDIO signals as far away as possible from the RF trace •...

  • Page 15: Uart Interface

    AN13125 NXP Semiconductors IW416 Design Guide 5.2 UART interface Figure 14 shows a typical application circuit for the UART interface. Figure 14. UART host interface connections AN13125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

  • Page 16: Rf Interface

    AN13125 NXP Semiconductors IW416 Design Guide RF interface The NXP reference designs for the Wireless SoC show the front-end configurations currently supported by NXP. It is recommended to discuss your desired front-end configuration with your NXP representative and have your design reviewed by NXP.
  • Page 17 AN13125 NXP Semiconductors IW416 Design Guide Figure 16 shows the filter circuit for Wi-Fi 2.4 GHz path. Figure 16. Discrete LPF on Wi-Fi 2.4GHz RF path Figure 17 shows the filter circuit for Bluetooth path. Figure 17. Discrete LPF on Bluetooth RF path For two antenna applications and where simultaneous 2.4 GHz Wi-Fi and Bluetooth...
  • Page 18 AN13125 NXP Semiconductors IW416 Design Guide Figure 18 shows the typical front-end topology for a single-antenna application. An external SPDT switch is required to combine the 2.4 GHz Wi-Fi and Bluetooth transmit/ receive paths. Use discrete low pass filters (LPF) to ensure the rejection of out-of-band emissions.

  • Page 19: Rf Front-End For Wlcsp Package

    AN13125 NXP Semiconductors IW416 Design Guide 6.2 RF front-end for WLCSP package Similar to QFN package, WLCSP package can also be configured as single or dual antenna front-end application. WLCSP package requires an external RF SPDT switch on 5 GHz Wi-Fi path to provide additional rejection to out-of-band emissions. The following RF front-end components must be used to reduce out-of-band emissions.
  • Page 20 AN13125 NXP Semiconductors IW416 Design Guide Figure 20 shows the circuit diagram for SPDT switch on Wi-Fi 5 GHz path. Figure 20. Circuit diagram for SPDT switch on Wi-Fi 5 GHz path Table 6 shows the list of recommended RF front-end components. Table 6. Recommended RF front-end components...
  • Page 21 AN13125 NXP Semiconductors IW416 Design Guide For single antenna designs, use the second SPDT switch to combine Wi-Fi 2.4 GHz and Bluetooth transmit/receive paths. Figure 21 shows a typical front-end topology for single antenna applications. Figure 21. RF front-end for single antenna application Use discrete low pass filters (LPF) to ensure the rejection of out-of-band emissions.

  • Page 22: Pcb Layout Guidelines

    AN13125 NXP Semiconductors IW416 Design Guide 6.3 PCB layout guidelines Refer to the following PCB layout guidelines for RF interface: • Route the RF signals on the top layer (micro strip) with 50 ohm impedance. • Reference the RF signals to a solid ground plane.
  • Page 23 AN13125 NXP Semiconductors IW416 Design Guide • Place stitching vias between the top and reference ground layers to increase isolation as shown in Figure Figure 23. Ground pour with stitching vias • Extend the ground plane between paths as much as possible. Extend the ground to the...
  • Page 24 AN13125 NXP Semiconductors IW416 Design Guide • RF trace to RF connector pad transition must be tapered to avoid discontinuity and high insertion loss, especially at 5 GHz band. An example is shown in Figure Figure 25. Taper line for RF trace to connector AN13125 All information provided in this document is subject to legal disclaimers.
  • Page 25 AN13125 NXP Semiconductors IW416 Design Guide • We recommend to place a non-plated through hole under the RF connector to minimize the insertion loss as shown in Figure Figure 26.  Non-plated through hole under the RF connector • Add a ground via on each side of RF via near the RF trace layer transition, the distance between the via and RF trace edge to edge is about 20 mil.
  • Page 26 AN13125 NXP Semiconductors IW416 Design Guide • For QFN package only, add a ground EPAD under the package for thermal relief as shown in Figure – Make sure the GND EPAD has a good number of thermal vias for the thermal path to be effective.
  • Page 27 AN13125 NXP Semiconductors IW416 Design Guide • For the WLCSP package only, do not route any signal traces, power planes, ground planes over the on-chip inductor keep-out areas. The on-chip inductor keep-out areas are highlighted in Figure Figure 28. On-chip inductor area under WLCSP package For additional details, refer to DXF drawing layer included in Wireless SoC WLCSP reference design PCB layout file on NXP website.

  • Page 28: Miscellaneous

    AN13125 NXP Semiconductors IW416 Design Guide Miscellaneous 7.1 Unused interfaces and pins Table 7 shows the PCB connection for unused pins. Table 7. Unused pins Pin name PCB connection when not used LDO_VIN Connect to ground LDO_VOUT Keep floating/No connect SLP_CLK_IN...

  • Page 29: Pcb Stackup

    AN13125 NXP Semiconductors IW416 Design Guide 7.3 PCB stackup • Ensure the stackup is symmetrical. • Ensure all layers meet specified thickness. • For WLCSP package, NXP reference design PCB typically consists of six layers with FR-4 material and blind buried vias.
  • Page 30 AN13125 NXP Semiconductors IW416 Design Guide • For QFN package, NXP reference design PCB can be of four to six layers with FR-4 material and plated through hole vias Figure 30 shows the typical six-layer PCB stack up for QFN package.

  • Page 31: Legal Information

    8.1 Definitions and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this Draft —...
  • Page 32 AN13125 NXP Semiconductors IW416 Design Guide Tables Tab. 1. Power supplies ..........4 Tab. 5. Recommended RF front-end components ..18 Tab. 2. MPS PMICs part numbers ........ 5 Tab. 6. Recommended RF front-end components ..20 Tab. 3. Marvell and NXP PMICs part numbers ..... 6 Tab.

  • Page 33: Table Of Contents

    'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 May 2021 Document identifier: AN13125...

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