Kenwood TK-885 Service Manual page 23

TK-885
Squelch Circuit
The detection output from the FM IF IC (IC11) is amplified
by IC2 and the signal (DEO) is sent to the control unit. The
signal passes through a high-pass filter and a noise amplifier
(Q503) in the control unit to detect noise. A voltage is ap-
plied to the CPU (IC511). The CPU controls squelch accord-
ing to the voltage (ASQ) level. The signal from the RSSI pin
of IC11 is monitored. The electric field strength of the re-
ceive signal can be known before the ASQ voltage is input to
the CPU, and the scan stop speed is improved.
CONTROL UNIT
IC2
IC11 AMP
DEO
IF
SYSTEM
RSSI
Fig. 5 Squelch circuit /
Transmitter System
Outline
The transmitter circuit produces and amplifies the desired
frequency directly. It FM-modulates the carrier signal by
means of a varicap diode.
VCO/PLL Circuit
The TK-885 has a VCO for the transmitter and a VCO for
the receiver in a sub-unit (A1). They are housed in a solid
shielded case and connected to the TX-RX unit through
CN101. One of the VCOs is selected with an ST signal. A
filtered low-noise power supply is used for the VCOs and
varicap diodes.
The VCO for the transmitter is described below. It is de-
signed so that Q103 turns on with a prescribed frequency
when a reverse bias is applied to D102 and D104 by using
the control voltage (CV) through CN101. The control voltage
22
CIRCUIT DESCRIPTION /
IC503 Q503
AMP NOISE AMP D509
HPF DET
is changed by turning the trimmer capacitor (IC109). The
output from Q103 is applied to the buffer amplifier (Q106) to
generate a VCO output signal. This signal is used as a drive
input signal or a local signal of the first mixer. Since a signal
output from Q160 is input to the PLL IC, it passes through
CN101 and buffer amplifier (Q300) and goes to the PLL IC
(IC300). The modulation signal from CN101 is applied to D105
and passes through C112 and C113 to modulate the carrier.
The PLL IC uses a fractional N type synthesizer to improve
the C/N ratio and lock-up speed. The VCO output signal in-
put to the pin 5 of the PLL IC is divided to produce a compari-
son frequency according to a channel step. This signal is
compared with the reference frequency which is output from
the VCXO (X1). VCXO provides 16.8MHz, 2.5ppm (D30 to
+60 C) and guarantees stable performance when the tem-
perature changes. The output signal from the phase com-
parator passes through a charge pump and an external ac-
tive LPF (Q301, Q302) in the PLL IC to generate a DC VCO
control voltage CV. Serial data (DT, CK, EP) are output from
the CPU (IC511) and shift register (IC8) in the control unit to
control the PLL IC. The PLL lock status is always monitored
by the CPU.
IC511
CPU