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Functions
Pin
Requirements
Supervision of
REG1
REG1 and REG2
REG2
Powersupply
VDD
supervision
VDDA supervision VDDA
Battery
temperature
supervision
Device
temperature
supervision
Analog switch
Outport
TWI Interface
TWI_CLK,
TWI_DATA,
TWI_INT
V1.20
A55/C55_Hitachi
Sequence
In active mode the regulators are supervised
permanently. If the voltage is under the
threshold, the pin
and the
mode. If the voltage is longer than Tmin under
threshold voltage, the RESET_N2 (PinG1) is
going to Low (Missing Watchdog signal ->
phone switched off). The level of regulator
REG1
permanently. If the voltage doesn't reach the
threshold value at switch on, the
(PinG1) will stay low and the
to power down mode. The voltages are sensed
continuously and digitally filtered with a time
constant Tmin. If the regulator voltage is under
threshold longer than Tmin, the
(PinG1) signal change to low and the µC will go
to RESET condition (Missing Watchdog signal -
> phone switched off).
If the battery voltage
high, everything is switched off immediately
within 1µs. Only the pull-up circuitry for the
external charge PMOS are active and will
discharge the gate of the external PMOS
To provide a short circuit protection at output of
VDDA
(PinA9) and output of stereo buffer a
voltage supervision is implemented. If the
VDDA output is less then this threshold, the
VDDA will be switched off for 128ms. After this
time the VDDA will be started again. The VDDA
supervision starts 60ms after startup of VDDA.
Charging is stopped, when over temperature
occurs. Within 128ms, 3 values are measured.
When these 3 values are identical status can
be changed. The supervision is active in fast
charge or trickle charge mode. Voltage on pin
TBAT
temperature increases. If Vbat < (Vref_exe -
Vhyst) charging is disabled. Only when Vtbatt >
Vref_exe charging is enabled again.
To protect the ASIC, the temperature is
supervised. The temperature is polled every
128ms and is filtered as in battery temperature
supervision. If over temperature is detected, a
bit in the STATUS register is set and an
interrupt is generated. Monitoring is started
only in active mode.
The
level
out_port_high of the TWI register. The high
level can be derived of VREG2 or VREG3.
Additional a pull down transistor is connected
to this node.
The TWI interface (I2CC-PinJ2, I2CD-PinG3,
I2CI-PinE2) is an I2C compatible 2-wire
interface with an additional interrupt pin to
inform the µC about special conditions.
The interface can handle clock rates up to 400
kHz.
Page 33 of 48
Company Confidential © Copyright Siemens AG
RESET_N2
(PinG1) stay Low
ASIC
goes back to the power down
and
REG2
will
ASIC
BATT+
(PinB3)
becomes
can
be
defined
be
supervised
RESET_N2
will go back
RESET_N2
exceeds VDD
smaller
when
by
the
bit
ICM MP CCQ GRM
04/03
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