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IC3401
(VENUS ENGINE)
IC601
(SUB LVDS:RX)
LCD LVDS0P
D0+
LVDS TX0P Y3
G1
LCD LVDS0N
D0-
LVDS TX0M
Y4
H1
LCD LVDS1P
D1+
LVDS TX1P AA1
C1
LCD LVDS1N
D1-
LVDS TX1M
AA2
D1
LCD LVDSCLKP
CLK+
LVDS TXCP
Y1
E1
LCD LVDSCLKN
CLK-
LVDS TXCM
Y2
F1
F/XS
PW REG1.8V
F2
LS0
D4
PSEL0
D3
FM
D5
FSS
E5
LS1
E4
PSEL1
E3
TX/RX
C2
XSD
G2
E LCD RST
GPIO399 AD6
S LCDEVF DO
GPIO264 Y23
S LCD CS
GPIO401 AF5
S LCDEVF SCK
GPIO262 W23
E EVF RST
GPIO400 AG5
S EVF CS
GPIO402 AE5
VSYNC RST
GPIO240 U23
CH3519
S2M RDY INT1
GPIO159
F18
CH3517
S2M REQ INT0
GPIO161 F19
CH3515
S BECPU SCK
GPIO155 F16
CH3513
S BECPU DO
GPIO157 F17
CH3511
S BECPU DI
GPIO156 G16
CH3509
S BECPU CS
GPIO157 F17
CH3520
S2M INT1
GPIO263
Y24
CH3518
S2M RDY INT0
GPIO265 AA24
CH3516
S CAMCPU SCK
GPIO258 V24
CH3512
S CAMCPU DI
GPIO259 V23
CH3514
S CAMCPU DO
GPIO260 W25
CH3510
S CAMCPU CS
GPIO261 W24
3
2
GND
IC3102
IC3101
(GATE IC)
(FPGA)
Y
4
IO L1P CCLK 2 N13
IC3103
(GATE IC)
IO L3P D0 DIN MISO MISO1 2 N11
R0
F6
LVOUT R0-7
R7
H5
G0
A7
LVOUT G0-7
G7
E7
N x PCLK
A3
B0
LVOUT B0-7
PLL
0
B7
B6
1
DDR
SDR
HS
H4
VS
FSS
G3
PCLK
G4
CONFIGURATION
AND
POWER MANAGEMENT
IC3501
(VENUS ENGINE)
U24
GPIO239
R6
GPIO35
R7
GPIO36
K2
GPIO25
K3
GPIO26
K4
GPIO27
J1
GPIO28
GPIO106
C13
D13
GPIO107
F12
GPIO108
G13
GPIO110
F13
GPIO109
F14
GPIO111
PW REG1.8V
1
B
A
VCC
5
PW REG1.8V
PW REG1.8V
3
2
1
GND
B
A
Y
VCC
4
5
PW REG1.8V
IC602
(SUB LVDS:TX)
D0+
B1
C7
R0
D0-
A5
R7
A1
D1+
F1
H7
G0
D1-
D6
G7
E1
H3
B0
CLK+
N x PCLK
D1
2
1
G6
B7
PLL
1 x PCLK
CLK-
0
C1
HS
A4
VS
FSS
B3
LS0
D4
PSEL0
D3
PCLK
PSEL1
B4
E3
TX/RX
CONFIGURATION
C2
AND
F/XS
POWER MANAGEMENT
F2
FM
D5
XSD
FSS
G2
E5
LS1
E4
IC603
(SUB LVDS:TX)
D0+
G1
C7
R0
D0-
A5
R7
H1
D1+
C1
H7
G0
D1-
D6
G7
D1
H3
B0
CLK+
N x PCLK
E1
2
1
G6
B7
PLL
1 x PCLK
CLK-
0
F1
HS
A4
VS
FSS
B3
LS0
D4
PSEL0
D3
PCLK
PSEL1
B4
E3
TX/RX
CONFIGURATION
C2
XSD
AND
G2
F/XS
POWER MANAGEMENT
F2
FM
D5
FSS
E5
LS1
E4
FL603
LCD D0 P
3
2
LCD D0 N
4
1
FL601
LCD D1 P
3
2
LCD D1 N
4
1
FL602
LCD CLK P
3
2
LCD CLK N
4
1
LCD
UNIT
PW REG1.8V
RST
S DO LCD
S CS LCD
S CLK LCD
S DO EVF
S CLK EVF
FL604
EVF D0 P
4
1
EVF D0 N
3
2
FL606
EVF D1 P
4
1
EVF D1 N
3
2
FL605
EVF
EVF CLK P
4
1
UNIT
EVF CLK N
3
2
PW REG1.8V
RST
S CS EVF
HC-X1000 VIDEO/AUDIO PROCESS ( 2 ) CIRCUIT BLOCK DIAGRAM
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