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7.0 Troubleshooting
7.1 Possible Issues
The following table assumes a transmitter and receiver device, correctly configured to transmit video over the
ADK. Please refer to [1] - APICO User Manual, Inova Semiconductors GmbH or [3] - INAP375T/R Usermanual,
Inova Semiconductors GmbH for further information regarding configuration.
Problem
Indicators
No picture
TX:
st_px_ch0_timgen_locked=1
RX:
st_px_ch0_synth_locked=1
st_px_ch0_timing_locked=1
st_px_ch0_clksyn_rdy=1
No picture
TX:
st_px_ch0_timgen_locked=0
RX:
st_px_ch0_synth_locked=0
7.2 Reset LVDS transmitters
After powering up the ADK board, or after changing the transmitter input clock of DS90C385, provide a 1 sec-
ond pulse of 0 Volts at PWR DOWN pin by short circuiting the jumper SJ1/SJ2 (depending on application).
"The transmitter input clock must always be present when the device is enabled (PWR DOWN = HIGH). If the
clock is stopped, the PWR DOWN pin must be used to disable the PLL. The PWR DOWN pin must be held low
until after the input clock signal has been reapplied. This will ensure a proper device reset and PLL lock to oc-
cur. The transmitter input clock may be applied prior to powering up and enabling the transmitter. The trans-
mitter input clock may also be applied after power up; however, the use of the PWR DOWN pin is required as
described in the Transmitter Input Clock section." (see datasheet of DS90C385)
UM_APIX2_ADK_TX (Rev2) Revision 1.2_A1
User Manual
Possible solution
Link transmits a video but isn't displayed correctly
Possible root cause: Wrong EDID
The default EDID provided with APICO might not
match the monitor in your setup. In case the picture
doesn't come out, it might be necessary to read
back the EDID for the monitor (connect the monitor
to the PC and read back the EDID using an EDID
tool) and use that EDID instead of the default EDID.
Please check the APICO User manual how to
change the EDID file for the HDMI inputs.
INAP375T doesn't receive a correct image. Please
check the video source, if it correctly detected the
APIX2_ADK as monitor and if the resolution and
video timing applied is within the limits of the
INAP375T timing analyzer. Additionally reset the
LVDS Transmitters as described in section 7.2
Table 7-9: Troubleshooting
Inova Semiconductors Confidential
Page 34 of 37
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