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2
J P 1
1
Figure 2 Diagram of JP1 (board revisions "A" to "F")
AVT-718 Signal
VPW bus
PWM bus +
PWM bus -
K-line
L-line
CAN - H
CAN - L
SWC
UBP / LIN
P3 pin #1
P3 pin #11
Table 1 Default Configuration of JP1 (board revisions "A" to "F")
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Edge of board
JP1 pin #
1
shunt
3
shunt
5
shunt
7
shunt
9
shunt
11
shunt
13
shunt
15
17
19
21
25
2 2
8
1 5
2 1
P 3
1
9
JP1 pin #
P3 pin #
2
2
4
2
6
10
8
7
10
15
12
6
14
14
16
9
18
3
20
8
22
12
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