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Curtiss-Wright Compact CHAMP-AV IV User Manual

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Summary of Contents for Curtiss-Wright Compact CHAMP-AV IV

  • Page 1 (217) 352-9330 | Click HERE Find the Curtiss-Wright CHAMP-AV IV / SVME-416 at our website:...
  • Page 2 Document Number: 814256 Version: Date: February 2006 CHAMP-AV IV OMPACT OWER (SCP-424) ’ ANUAL Curtiss-Wright Controls Embedded Computing 333 Palladium Drive Ottawa, Ontario, Canada K2V 1A6 (613) 599-9199 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 3 The information in this document is subject to change without notice and should not be construed as a commitment by Curtiss-Wright Controls, Inc. While reasonable precautions have been taken, Curtiss-Wright Controls, Inc. assumes no responsibility for any errors that may appear in this document.

  • Page 4: Table Of Contents

    URTISS RIGHT ONTROLS MBEDDED OMPUTING ABLE OF ONTENTS 1. Product Overview ....................... 1-1 General Description ......................1-2 Feature Summary......................... 1-4 Technical Description ......................1-4 QuadFlow Architecture..................... 1-5 Processor Nodes ......................1-5 Node E Processor ......................1-6 Double Data Rate SDRAM....................1-6 Flash Memory .........................
  • Page 5 ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING Configuring an Emulator for use with Compact CHAMP-AV IV..........3-8 Troubleshooting ........................3-10 Verify Insertion in Chassis ....................3-10 FAIL LED Behavior ......................3-10 Sign-on Message Garbled ....................3-10 The Next Step ........................3-10 4. Programming Interface ....................4-1 Compact CHAMP-AV IV Memory Map ..................
  • Page 6 URTISS RIGHT ONTROLS MBEDDED OMPUTING IST OF IGURES Figure 1.1: Compact CHAMP-AV IV Functional Block Diagram ............. 1-3 Figure 1.2: Processor Node Block Diagram................1-5 Figure 1.3: cOBIC Block Diagram ................... 1-9 Figure 1.4: Interrupt Routing ....................1-10 Figure 1.5: Interrupt Structure.....................
  • Page 7 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING 814256 V 2006 ERSION EBRUARY Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 8 Table 1.5: Serial Port Summary ..................1-17 Table 1.6: Timing Resources....................1-19 Table 1.7: Summary of Compact CHAMP-AV IV Connectors, Functions Supported ...... 1-24 Table 1.8: Compact CHAMP-AV IV Dimensions ..............1-24 Table 1.9: Compact CHAMP-AV IV Weight ................1-25 Table 2.1:...
  • Page 9 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING 814256 V 2006 VIII ERSION EBRUARY Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 10 REFACE URPOSE This manual describes the cPCI based Compact CHAMP-AV IV. After explaining the capabilities of the Compact CHAMP-AV IV, the manual provides the procedure for correctly installing it and checking its operation. UDIENCE This document is aimed at readers with a technical understanding of hardware engineering fundamentals, as well as a basic understanding of the cPCI, PCI, and digital signal processing hardware and software.
  • Page 11 This manual contains the following chapters: Chapter 1 - Product Overview. This chapter provides an overview of the features and functions of the Compact CHAMP-AV IV. This includes a technical description of the block diagram. Chapter 2 - Pre-Installation Tasks. This chapter discusses tasks that must be performed before installing the Compact CHAMP-AV IV in a system, including checking power requirements.
  • Page 12 URTISS RIGHT ONTROLS MBEDDED OMPUTING Typographic Conventions ABLE Item Convention Example Keystrokes Keys are listed as they appear on most keyboards, Type < Ctrl-Alt-C > to return to the previous menu. surrounded by < > marks. Combinations of key- Type < Esc > to exit. strokes appear within a single set of <...
  • Page 13 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING Signal Table 2 lists symbols that can follow a signal name. For example, the Hash (#) is used with a Conventions PCI or cPCI signal name, such as FRAME#. Signal Conventions ABLE Symbol...
  • Page 14 URTISS RIGHT ONTROLS MBEDDED OMPUTING EFERENCE OCUMENTATION Refer to the following standards for information about the specifications the Compact CHAMP-AV IV is designed for compliance with: • IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC), IEEE Std 1386.1-2001, June 14, 2001 •...
  • Page 15 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING 814256 V 2006 ERSION EBRUARY Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 16 RODUCT VERVIEW HAPTER This chapter discusses the high-level features of the Compact CHAMP-AV IV product. The following topics are discussed: • “General Description” on page 1-2 • “Feature Summary” on page 1-4 • “Technical Description” on page 1-4 – “QuadFlow Architecture” on page 1-5 –...
  • Page 17 The Compact CHAMP-AV IV also has a powerful fifth processor, the Freescale MPC8540 PowerQUICC III. The Compact CHAMP-AV IV is particularly well suited to large, multi-slot systems. This is by virtue of its four 800 MB/sec (peak) PCI buses and its five Gigabit Ethernet connections (one per processor), which together provide very high I/O throughput and switching bandwidth.

  • Page 18: Product Overview

    URTISS RIGHT ONTROLS MBEDDED OMPUTING RODUCT VERVIEW 1.1: Compact CHAMP-AV IV Functional Block Diagram IGURE Local Local SDRAM SDRAM (256 MB - (256 MB - 512 MB) 512 MB) 64-bit MPC7447 64-bit up to 64-bit MPC7447 MV64460 MV64460 133 MHz...

  • Page 19: Feature Summary

    Image VSIPL DSP library • air-cooled level 0 ruggedization ECHNICAL ESCRIPTION The operation of the Compact CHAMP-AV IV is described in the following sections, with reference to the high level block diagram illustrated in Figure 1.1. 814256 V 2006 ERSION EBRUARY Artisan Technology Group - Quality Instrumentation ...

  • Page 20: Processor Nodes

    VERVIEW RCHITECTURE The Compact CHAMP-AV IV architecture is suited to DSP applications that place a high premium on processor to memory, processor to processor, and PMC I/O to memory bandwidth. The data flow capabilities of the Compact CHAMP-AV IV ensure that applications can extract the most from the raw computing performance of the four AltiVec engines.

  • Page 21: Nodee Processor

    The memory map of the Compact CHAMP-AV IV allows any processor to access the memory of any other processor and both PMC sites. Any PMC module can access any of the processor node memories.

  • Page 22: Flash Memory

    LASH EMORY The Compact CHAMP-AV IV provides 32, 64, 128 or 256 MBytes of 32-bit Flash memory on node A. The Flash devices are specified for 100,000 erase cycles per sector (typical) and a data retention time of 20 years (typical).

  • Page 23: Pci Local Bus

    PCI L OCAL The Compact CHAMP-AV IV contains four local PCI buses. The four buses are interconnected through the PCI-X to PCI-X bridging capability of the Discovery III bridges. The PCI buses connect Nodes A, B, C and D in a ring architecture and operate at a maximum rate of 100 MHz, 64 bits (800 MBytes/s).

  • Page 24: Figure 1.3: Cobic Block Diagram

    RODUCT VERVIEW The Compact CHAMP-AV IV also contains an alternate serial PROM which can be used to configure the cOBIC in the event that there is a problem with the main PROM. This PROM is not upgradeable by the customer and puts the cOBIC into a known working state. Switch SW4 is used to select the main PROM and the alternate PROM (see “Configuring Switches”...

  • Page 25: Figure 1.4: Interrupt Routing

    In a multi-processor system, a fixed mapping of hardware interrupts to specific processors is likely to be less then optimum. The Compact CHAMP-AV IV allows the hardware to adapt to the needs of the software. All of the internal and external interrupt sources (PMC modules, GPIO, PCI, etc.) are routed into a software-configurable multiplexer that allows...
  • Page 26 URTISS RIGHT ONTROLS MBEDDED OMPUTING RODUCT VERVIEW 1.1: Internal Interrupt Sources ABLE Interrupt Input Detection Mode Location for Description Clearing FIFO Not Empty [A:E] N/A cOBIC There is a 16-bit, 32 Deep FIFO associated with each processor. When one of these FIFO's receives data, it produces an interrupt.
  • Page 27 The problem with this mechanism is that many board architectures suffer latencies and other slowdowns because the same PCI bus that is used for inter-processor data transfers is also used for passing these interrupts. The Compact CHAMP-AV IV has special purpose hardware to accelerate inter-processor messaging. This hardware is contained in the inter-processor module and consists of processor to processor mailbox interrupts and hardware-controlled interrupt routing facilities.
  • Page 28 URTISS RIGHT ONTROLS MBEDDED OMPUTING RODUCT VERVIEW a six-bit value is written to the IPI register. This causes the Inter-Processor Interrupt Status register to be updated for the target processor. The Inter-Processor Interrupt Status register for the target processor reflects the decoded Processor Identification value. For instance, processor A writing a binary 0001_0011 to its IPI register causes Processor Identification bit 3 to be set in Processor B Interrupt Status register.
  • Page 29 Avionics Style The Compact CHAMP-AV IV provides five watchdog timers, one for each processor. Each Watchdog Timer watchdog timer is a presettable up counter with a resolution of approximately 970 ns. Time- out periods from 1 µs to 16 seconds can be programmed. Initialization software can select whether a watchdog exception event causes an interrupt, a local processor reset, or a card reset.
  • Page 30 At this point, the watchdog timer will halt. To clear the interrupt, clear the WDT_EN bit. General Purpose The Compact CHAMP-AV IV provides eight additional general purpose LVTTL I/O lines which I/O and Interrupt are accessible at the J4 connector. The GPIO signals may be configured individually to be Inputs inputs or outputs.

  • Page 31: Figure 1.6: Led Control

    LEDs located on the back of the board (see Figure 1.9 on page 1-22). All of the Compact CHAMP-AV IV surface mount LEDs can be controlled by any of the processors writing to the Global LED register. Further, each of the processors has a processor LED register that controls the green processor status LED and two of the surface mount status LEDs.

  • Page 32: Compact Pci Interface

    RODUCT VERVIEW PCI I OMPACT NTERFACE The Compact CHAMP-AV IV does not have an interface to the Compact PCI backplane. The only signals on J1 and J2 that are used are reset, BDSEL, HEALTHY# and geographical addressing. ERIAL ORTS The Compact CHAMP-AV IV provides two EIA-232 asynchronous serial ports, one on Node A and the other on Node E.

  • Page 33: Ethernet Interfaces

    OMPUTING THERNET NTERFACES The Compact CHAMP-AV IV has five Gigabit Ethernet interfaces, one per processor. Processors A-D (MPC7447A/7448) use the Gigabit Ethernet MAC located in their associated MV64660 (Discovery III) bridge. There are two Ethernet interfaces per Discovery III, Ethernet 0 and Ethernet 1. Only Ethernet 0 is used. The Discovery III bridge implements a number of features that are designed to minimize processor loading due to Ethernet traffic.

  • Page 34: Reset

    Individual processor reset through the Boot Monitor. • cPCI system reset IMERS The Compact CHAMP-AV IV board provides a large number of timing resources to facilitate precise timing and control of system events. A list of available timers is given in Table 1.5 below. 1.6:...

  • Page 35: Cop Interface

    COP I NTERFACE The Compact CHAMP-AV IV COP signals utilize 3.3 V signaling and are available on the J4 connector. When connecting an emulator to these signals, the emulator must be configured for 3.3 V signaling. The COP interface is accessible via the: Improper connection of the emulator can damage the Compact CHAMP-AV IV board and/or the emulator.

  • Page 36: Physical Characteristics

    HYSICAL HARACTERISTICS Figure 1.8 shows the location of the major components and the mating connectors on the top side of the Compact CHAMP-AV IV. All ruggedization levels of the board have a thermal shunt that covers some of the components.
  • Page 37 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING 1.9: Bottom View of Compact CHAMP-AV IV PWB IGURE Q212 Q213 Q214 U221 U226 U233 Q204 Q207 Q208 Q217 D210 TP205 U205 TP204 U204 Q209 Q210 Q211 Q215 Q216...

  • Page 38: Front Panel

    OMPUTING RODUCT VERVIEW SCP-424 An illustration showing the front panel that is mounted on the Compact CHAMP-AV IV (also known as the SCP-424) is provided below, along with a brief description of the indicators and Front Panel connectors it provides.

  • Page 39: Mating Connectors

    Windows utility generates the P0 and P2 pinouts based on the I/O configuration of the Compact CHAMP-AV IV and the PMC modules installed on it. IMENSIONS Table 1.8 lists the physical dimensions of the Compact CHAMP-AV IV. 1.8: Compact CHAMP-AV IV Dimensions...

  • Page 40: Weight

    URTISS RIGHT ONTROLS MBEDDED OMPUTING RODUCT VERVIEW EIGHT Table 1.9 lists the weight of the Compact CHAMP-AV IV. 1.9: Compact CHAMP-AV IV Weight ABLE Card Type Weight Compact CHAMP-AV IV (est. 1.3 lbs - TBD) 814256 V 2006 1-25 ERSION EBRUARY Artisan Technology Group - Quality Instrumentation ...

  • Page 41: Overview Of Available Software

    YSTEM OFTWARE The Compact CHAMP-AV IV is supported with an extensive array of software items, which cover all facets of developing application code for the board. Users have the option of choosing to develop with a variety of operating systems and development tools. The following operating systems are supported on the Compact CHAMP-AV IV: •...

  • Page 42: Optimized Dsp Libraries

    CHAMP-AV IV board through the Ethernet port. It is used to display and modify board configuration information, upgrade board software, and load application code. Wind River The Compact CHAMP-AV IV supports the use of the Wind Power ICE emulator (or equivalent) Systems Vision via COP signals which are presented on the backplane connectors.
  • Page 43 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING 1-28 814256 V 2006 ERSION EBRUARY Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 44: Pre-Installation Tasks

    NSTALLATION ASKS HAPTER This chapter discusses the following topics: • “Unpacking the Card” on page 2-2 • “Checking Hardware Requirements” on page 2-2 – “Chassis Requirements” on page 2-2 – “Power Requirements” on page 2-2 – “Flash Configuration Parameters” on page 2-4 –...
  • Page 45 CD-ROM and also available on www.dy4.com) for more information. Cross Reference OWER EQUIREMENTS The Compact CHAMP-AV IV requires +5 V and +3.3 V power supplies in order to operate. Table 2.1 shows the power requirements for the Compact CHAMP-AV IV. 814256 V 2006...
  • Page 46 3. Values available 1Q06. 4. The ± 12V supplies are not used by the Compact CHAMP-AV IV circuitry, however they are routed to the PMC sites on the board, therefore the current drawn from these supplies is PMC module-dependent.

  • Page 47: Flash Configuration Parameters

    Nodes B and C. See Figure 1.8 on page 1-21 for an illustration of the Compact CHAMP-AV IV board layout. Each PMC site can be independently configured at the factory to support either 3.3V or 5V signaling on their PCI bus.

  • Page 48: Figure 2.1: Position Of 5V And 3.3V Keying Holes On A Pmc Board

    J3 and J5 cPCI bus connectors. The backplane I/O for PMC Site 1 (mounted between Nodes A and D) is routed out the Compact CHAMP-AV IV cPCI bus J5 connector. The backplane I/O for the PMC Site 2 (mounted between Nodes B and C) is routed out the Compact CHAMP-AV IV cPCI J3 connector.
  • Page 49 The RESETOUT# signal (Jn2 pin 60) is an active low, open drain output from the PMC. When asserted by the PMC, the Compact CHAMP-AV IV will perform a board reset (same as pushing the reset switch on the Compact CHAMP-AV IV board).
  • Page 50 OMPUTING NSTALLATION ASKS PMC Module The Compact CHAMP-AV IV supplies 5V, 3.3V, VIO, +12V, and -12V power to the PMC sites. Power According to the PMC specification, the maximum power dissipation allowed for each PMC Considerations site is 7.5 Watts (see Table 2.4). The Compact CHAMP-AV IV is designed to follow this specification and in some cases, exceed it.

  • Page 51: Configuring Switches

    Switch Definition ABLE Switch Default User-defined. Switches are read by software on the Compact CHAMP-AV IV and left up to the S2[1] - S2[3] application. S2[4] Alternate FPGA PROM is used to program FPGA Main FPGA PROM is used program FPGA...
  • Page 52 URTISS RIGHT ONTROLS MBEDDED OMPUTING NSTALLATION ASKS 2.2: Configuration Switch Locations IGURE TH21 TH22 C137 C138 C139 C140 C141 TH26 TH25 TH24 TH23 C143 C142 R102 R104 R103 R105 TH36 C144 C145 C146 C147 C148 C149 C1282 TH31 TH37 C105 C104 TH32 C100...
  • Page 53 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING 2-10 814256 V 2006 ERSION EBRUARY Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 54: Hardware Installation

    – “Running the Boot Monitor” on page 3-6 – “Initiate the Power-Up Sequence” on page 3-6 – “Display the Initial Screen Message” on page 3-6 – “Configuring an Emulator for use with Compact CHAMP-AV IV” on page 3-8 • “Troubleshooting” on page 3-10 –...
  • Page 55 Boot Monitor and the PBIT capabilities. Cross Reference NSTALLATION REREQUISITES Before installing the Compact CHAMP-AV IV in your chassis, please take a moment to review the following items and planning considerations: NSTALLATION HECKLIST Make sure you have the following items before proceeding with the installation: •...

  • Page 56: Install The Pmc Modules On The Basecard

    The Compact CHAMP-AV IV does not support cPCI System Slot capability, therefore it cannot be installed in the System Slot (usually marked off by different color card guides.) Additionally, in a PICMG 2.16 chassis, the Compact CHAMP-AV IV is considered a Node board and must be installed in a PCIMG 2.16 Node slot.

  • Page 57: Quick Installation And Power Up Procedure

    Inhibit mode, which prevents the board from loading the operating system, but allows it to interact with the serial port. 2. With power off, install the Compact CHAMP-AV IV into the chassis. Ensure the cPCI connectors are fully engaged. 3. Install CWCEC or custom RTM in the back of the cPCI chassis. The RTM must be installed in the same slot as the Compact CHAMP-AV IV.

  • Page 58: Detailed Installation Procedure

    1 stop bit). Flow control is via software (xon/xoff). ONNECT THERNET Connect Ethernet Port E of the Compact CHAMP-AV IV to your Ethernet LAN via the connector labelled "ENET E" on the RTM. Ethernet Port E is used in conjunction with the CHAMPtools Software Update Utility to burn programs into Flash memory on the Compact CHAMP-AV IV.

  • Page 59: Running The Boot Monitor

    This section describes the normal power-up behavior of the Compact CHAMP-AV IV. The Compact CHAMP-AV IV Flash memory is managed by the A processor. As a result, processor A plays a unique role during board boot-up. After power-on or board reset, processor A loads and executes the Boot Monitor program stored in Flash memory.
  • Page 60 URTISS RIGHT ONTROLS MBEDDED OMPUTING ARDWARE NSTALLATION CHAMPtools Boot Monitor Version 3.0000, Feb 18 2005 13:28:41 Copyright, 2002-2004, Dy 4 Systems, Inc. JMP: Boot-inhibit mode Transitioning to bootMon2.exe... CHAMPtools Boot Monitor Version 3.0000, Feb 18 2005 13:28:41 Copyright, 2002-2004, Dy 4 Systems, Inc. Board: Compact CHAMP AV-IV Board:...

  • Page 61: Ersion Ebruary

    A PowerPC 74xx or 8540 emulator may be used to interact with each processor and the board hardware on the Compact CHAMP-AV IV card. A COP connection is provided on the RTM for this purpose. When connecting an emulator to the RTM, make sure that pin one of the emulator pod aligns with pin one on the RTM connector.
  • Page 62 "go". Make sure that the signaling level on the emulator pod connected to the COP interface on the Compact CHAMP-AV IV is set to 3.3V. Failure to do so could cause damage to the baseboard or the emulator.

  • Page 63: Troubleshooting

    FAIL LED B EHAVIOR The front panel Fail LED indicates the health of the Compact CHAMP-AV IV board. The illumination pattern of this LED at power-up or reset will differ depending upon the boot mode of the board. If the board is in either of the Normal Boot Modes, the Fail LED will...

  • Page 64: Programming Interface

    ROGRAMMING NTERFACE HAPTER This chapter contains the following information: • “Compact CHAMP-AV IV Memory Map” on page 4-2 – “Data Flow Directions” on page 4-4 814256 V 2006 ERSION EBRUARY Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 65: Compact Champ-Av Iv Memory Map

    EMORY The resources on the Compact CHAMP-AV IV are connected via four unique PCI buses. Since all nodes of the Compact CHAMP-AV IV are connected together by the PCI buses, all memory on the board is globally accessible. Each processor has a specific view of the board. Differences from one processor's view to...
  • Page 66 URTISS RIGHT ONTROLS MBEDDED OMPUTING ROGRAMMING NTERFACE 4.1: Compact CHAMP-AV IV Memory Map ABLE Address Range Size Processor Processor Processor Processor Processor PMC DMA 0000_0000 - 1FFF_FFFF 512 MB local mem local mem local mem local mem local mem illegal...

  • Page 67: Data Flow Directions

    ONTROLS MBEDDED OMPUTING 1. The Compact CHAMP-AV IV supports up to 512 MB of local SDRAM memory per node. When ordered with less than 512 MB of local SDRAM memory, the local memory space always begins at address 0000_0000. 2. Only the first 256 MB of local memory is accessible by other PCI devices on the PCI bus. This corresponds to local SDRAM space 0000_0000 through 0FFF_FFFF.
  • Page 68 URTISS RIGHT ONTROLS MBEDDED OMPUTING ROGRAMMING NTERFACE 4.1: Data Access Directions for Processor Nodes IGURE PMC1 PMC2 PMC1 PMC2 Resource Access Resource Access Directions for Node B Directions for Node A PMC2 PMC1 PMC1 PMC2 Resource Access Resource Access Directions for Node C Directions for Node D 814256 V 2006...

  • Page 69: Figure 4.2: Data Access Directions For Pmcs

    CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING 4.2: Data Access Directions for PMCs IGURE PMC1 PMC2 PMC2 PMC1 Resource Access Resource Access Directions for PMC2 Directions for PMC1 PMC2 PMC1 Resource Access Directions for Processor E 814256 V 2006 ERSION...

  • Page 70: Connector Pin Assignments

    ONNECTOR SSIGNMENTS PPENDIX This appendix provides the interface pinout information for each of the connectors on the Compact CHAMP-AV IV. The following connectors are described: • “J1 Connector Pin Assignments” on page A-2 • “J2 Connector Pin Assignments” on page A-4 •...

  • Page 71: J1 Connector Pin Assignments

    A.1: J1 Connector IGURE J1 and J4 Connector Rear View Table A.1 on page A-3 shows which signals are available from the J1 connector of the Compact CHAMP-AV IV. 814256 V 2006 ERSION EBRUARY Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 72: Electrical Characteristics Of J1 Signals

    Pull up on PWB, tied low or left floating on backplane. When low indicates GND or floating on that the backplane supports a Compact PCI bus. Signal is not currently backplane. used on the Compact CHAMP-AV IV. HEALTHY# Output Active low signal indicates that on-board power is up and within open-drain specification.

  • Page 73: J2 Connector Pin Assignments

    A.2: J2 Connector IGURE J2 and J5 Connector Rear View Table A.3 on page A-5 shows which signals are available from the J2 connector of the Compact CHAMP-AV IV. 814256 V 2006 ERSION EBRUARY Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 74: Electrical Characteristics Of J2 Signals

    URTISS RIGHT ONTROLS MBEDDED OMPUTING A.3: J2 Connector Pin Assignments ABLE Pin Number Row E Row D Row C Row B Row A V(I/O) V(I/O) V(I/O) V(I/O) V(I/O) V(I/O) J2 S LECTRICAL HARACTERISTICS OF IGNALS Table A.4 provides the electrical characteristics of the J2 signals. A.4: J2 Connector Description ABLE...

  • Page 75: J3 Connector Pin Assignments

    CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING J3 C ONNECTOR SSIGNMENTS Table A.5 lists the J3 pin assignments for the basecard. Figure A.3 shows the location of contacts on the J3 connector. A.3: J3 Connector IGURE J3 Connector Rear View Note: The pinout tables are presented in the order of the rows when looking from the backplane, (i.e.

  • Page 76: Electrical Characteristics Of J3 Signals

    URTISS RIGHT ONTROLS MBEDDED OMPUTING A.5: J3 Connector Pin Assignments ABLE Pin Number Row E Row D Row C Row B Row A SGA0 SGA1 SGA2 SGA3 SGA4 AD0-TRX2- AD0-TRX2+ AD0-TRX0- AD0-TRX0+ AD0-TRX3- AD0-TRX3+ AD0-TRX1- AD0-TRX1+ BD0-TRX2- BD0-TRX2+ BD0-TRX0- BD0-TRX0+ BD0-TRX3- BD0-TRX3+ BD0-TRX1-...

  • Page 77: J4 Connector Pin Assignments

    CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING J4 C ONNECTOR SSIGNMENTS The pinout tables are presented in the order of the rows when looking from the backplane, (i.e. E, D, C, B, A). Figure A.4 shows the location of the contacts on the J4 connector. A.4: J4 Connector IGURE J1 and J4 Connector...

  • Page 78: Electrical Characteristics Of J4 Signals

    URTISS RIGHT ONTROLS MBEDDED OMPUTING A.7: J4 Connector Pin Assignments ABLE Pin No. Row E Row D Row C Row B Row A GPIO3 GPIO2 GPIO1 GPIO0 GPIO7 GPIO6 GPIO5 GPIO4 -12V ED0-TRX2- ED0-TRX2+ ED0-TRX0- ED0-TRX0+ ED0-TRX3- ED0-TRX3+ ED0-TRX1- ED0-TRX1+ DD0-TRX2- DD0-TRX2+ DD0-TRX0-...

  • Page 79: J5 Connector Pin Assignments

    CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING J5 C ONNECTOR SSIGNMENTS Table A.9 lists the J5 pin assignments for the basecard. Figure A.5 shows the location of contacts on the J5 connector. A.5: J5 Connector IGURE J2 and J5 Connector Rear View Note: The pinout tables are presented in the order of the rows when looking from the backplane, (i.e.

  • Page 80: Electrical Characteristics Of J5 Signals

    URTISS RIGHT ONTROLS MBEDDED OMPUTING A.9: J5 Connector Pin Assignments ABLE Pin Number Row E Row D Row C Row B Row A A_232TX A_232RX E_232TX E_232RX LD_RXN3 LD_RXP3 LD_TXN3 LD_TXP3 LD_RXN2 LD_RXP2 LD_TXN2 LD_TXP2 LD_RXN1 LD_RXP1 LD_TXN1 LD_TXP1 LD_RXN0 LD_RXP0 LD_TXN0 LD_TXP0...

  • Page 81: Pmc Connectors

    OMPUTING PMC C ONNECTORS The Compact CHAMP-AV IV PMC connectors are described in the following sections. The direction of the signals in the tables describing the PMC Jn1 through Jn4 connectors is from the point of view of the baseboard.

  • Page 82: J11 Connector

    URTISS RIGHT ONTROLS MBEDDED OMPUTING J11 C ONNECTOR Table A.11 lists the pin assignments for the connector referenced J11. This connector is part of PMC site #1, and is referenced as Pn1/Jn1 in the PMC specification IEEE 1386.1-2001. A.11: J11 Connector Description (Pn1/Jn1 64-bit PCI) ABLE Pin No.
  • Page 83 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING A.11: J11 Connector Description (Pn1/Jn1 64-bit PCI) (Continued) ABLE Pin No. Signal Direction Description Electrical Characteristics AD[17] PCI Address/Data Bus PCI/PCI-X FRAME* PCI Cycle Frame Signal PCI/PCI-X IRDY* PCI Initiator Ready Signal PCI/PCI-X DEVSEL* PCI Device Select Signal...

  • Page 84: J12 Connector

    URTISS RIGHT ONTROLS MBEDDED OMPUTING J12 C ONNECTOR Table A.12 lists the pin assignments for the connector referenced J12. This connector is part of PMC site #1, and is referenced as Pn2/Jn2 in the PMC specification IEEE 1386.1-2001. A.12: J12 Connector Description (Pn2/Jn2 64-bit PCI) ABLE Pin No.
  • Page 85 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING A.12: J12 Connector Description (Pn2/Jn2 64-bit PCI) (Continued) ABLE Pin No. Signal Direction Description Electrical Characteristics C/BE[2]* PCI Command/Byte Enable Bus PCI/PCI-X IDSELB IDSELB for second PCI agent PCI/PCI-X TRDY* PCI Target Ready PCI/PCI-X...

  • Page 86: J13 Connector

    URTISS RIGHT ONTROLS MBEDDED OMPUTING J13 C ONNECTOR Table A.13 lists the pin assignments for the connector referenced J13. This connector is part of PMC site #1, and is referenced as Pn3/Jn3 in the PMC Specification IEEE 1386.1-2001. A.13: J13 Connector Description (Pn3/Jn3 64-bit PCI) ABLE Pin No.
  • Page 87 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING A.13: J13 Connector Description (Pn3/Jn3 64-bit PCI) (Continued) ABLE Pin No. Signal Name Direction Description Electrical Characteristics AD[48] PCI Address/Data Bus PCI/PCI-X AD[47] PCI Address/Data Bus PCI/PCI-X AD[46] PCI Address/Data Bus PCI/PCI-X AD[45] PCI Address/Data Bus...

  • Page 88: J14 Connector

    URTISS RIGHT ONTROLS MBEDDED OMPUTING J14 C ONNECTOR Table A.14 lists the pin assignments for the connector referenced J14. This connector is part of PMC site #1, and is referenced as Pn4/Jn4 in the PMC specification IEEE 1386.1-2001. A.14: J14 Connector Description (Pn4/Jn4 User Defined I/O) ABLE J14 Pin cPCI J5 Pin Number...
  • Page 89 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING A.14: J14 Connector Description (Pn4/Jn4 User Defined I/O) (Continued) ABLE J14 Pin cPCI J5 Pin Number Direction Description Electrical Characteristics PMC #1 connection to cPCI J5 connector Depends on module PMC #1 connection to cPCI J5 connector Depends on module PMC #1 connection to cPCI J5 connector...

  • Page 90: J21 Connector

    URTISS RIGHT ONTROLS MBEDDED OMPUTING J21 C ONNECTOR Table A.15 lists the pin assignments for the connector referenced J21. This connector is part of PMC site #2, and is referenced as Pn1/Jn1 in the PMC Specification IEEE 1386.1-2001. A.15: J21 Connector Description (Pn1/Jn1 64-bit PCI) ABLE Pin No.
  • Page 91 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING A.15: J21 Connector Description (Pn1/Jn1 64-bit PCI) (Continued) ABLE Pin No. Signal Name Direction Description Electrical Characteristics AD[17] PCI Address/Data Bus PCI/PCI-X FRAME* PCI Cycle Frame Signal PCI/PCI-X IRDY* PCI Initiator Ready Signal PCI/PCI-X DEVSEL*...

  • Page 92: J22 Connector

    URTISS RIGHT ONTROLS MBEDDED OMPUTING J22 C ONNECTOR Table A.16 lists the pin assignments for the connector referenced J22. This connector is part of PMC site #2, and is referenced as Pn2/Jn2 in the PMC specification IEEE 1386.1-2001. A.16: J22 Connector Description (Pn2/Jn2 64-bit PCI) ABLE Pin No.
  • Page 93 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING A.16: J22 Connector Description (Pn2/Jn2 64-bit PCI) (Continued) ABLE Pin No. Signal Name Direction Description Electrical Characteristics C/BE[2]* PCI Command/Byte Enable Bus PCI/PCI-X IDSELB IDSELB for second PCI agent PCI/PCI-X TRDY* PCI Target Ready...

  • Page 94: J23 Connector

    URTISS RIGHT ONTROLS MBEDDED OMPUTING J23 C ONNECTOR Table A.17 lists the pin assignments for the connector referenced J23. This connector is part of PMC site #2, and is referenced as Pn3/Jn3 in the PMC Specification IEEE 1386.1-2001. A.17: J23 Connector Description (Pn3/Jn3 64-bit PCI) ABLE Pin No.
  • Page 95 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING A.17: J23 Connector Description (Pn3/Jn3 64-bit PCI) (Continued) ABLE Pin No. Signal Name Direction Description Electrical Characteristics AD[48] PCI Address/Data Bus PCI/PCI-X AD[47] PCI Address/Data Bus PCI/PCI-X AD[46] PCI Address/Data Bus PCI/PCI-X AD[45] PCI Address/Data Bus...

  • Page 96: J24 Connector

    URTISS RIGHT ONTROLS MBEDDED OMPUTING J24 C ONNECTOR Table A.18 lists the pin assignments for the connector referenced J24. This connector is part of PMC site #2, and is referenced as Pn4/Jn4 in the PMC specification IEEE 1386.1-2001. A.18: J24 Connector Description (Pn4/Jn4 User Defined I/O) ABLE J24 Pin No.
  • Page 97 CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING A.18: J24 Connector Description (Pn4/Jn4 User Defined I/O) (Continued) ABLE J24 Pin No. cPCI J5, J3 Pin Direction Description Electrical Number Characteristics PMC #2 connection to cPCI J3 connector Depends on module PMC #2 connection to cPCI J3 connector Depends on module...

  • Page 98: Pmc To Cpci Connector Mapping For Differential Signaling

    URTISS RIGHT ONTROLS MBEDDED OMPUTING PCI C TO C ONNECTOR APPING FOR IFFERENTIAL IGNALING A.19: PMC to cPCI Connector Mapping for Differential Signaling ABLE J14 to cPCI J14 Pins cPCI J5 Pins J24 to cPCI J24 Pins cPCI J3/J5 Pins Pair # (PMC Site 1) Pair #...

  • Page 99: Pmc To Cpci Connector Mapping For Single-Ended Signaling

    CHAMP-AV IV U ’ OMPACT ANUAL URTISS RIGHT ONTROLS MBEDDED OMPUTING PCI C TO C ONNECTOR APPING FOR INGLE NDED IGNALING A.20: PMC to cPCI Connector Mapping for Single-Ended Signaling ABLE J14/J24 cPCI J5 Pins cPCI J3/J5 Pins J14/J24 cPCI J5 Pins cPCI J3 Pins Pin # (PMC Site 1)

  • Page 100: Index

    Index block diagram 1-3 hardware requirements 2-2 bottom view, Compact CHAMP-AV IV PWB 1-22 high speed SRAM 1-7 Built In Test (BIT) firmware 1-26 indicator LEDs 1-16 CHAMP-AV IV memory map 4-2 initial screen message 3-6 chassis requirements 2-2, 2-5...
  • Page 101 1-17 Sign-on Message Garbled 3-10 slot location 3-3 software development tools 1-27 software overview 1-26 summary of Compact CHAMP-AV IV connectors 1- SVME-424 Front Panel 1-23 technical description 1-4 temperature/voltage sensors 1-19 terminal settings 3-10 The Next Step 3-10...

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