Sony STR-DA2800ES Service Manual page 161

Pin No. Pin Name
AD3 USB_2P_VRT
AD4 NFREN
AD5 NFCEN2
AD6 GPIO4
AD7 TCK
AD8 TDI
AD9,
RDQM3, RDQM2
AD10
AD12 RDQ23
AD13 RA0
AD14 RCAS_
AD15 to RA5, RA13,
AD18 RA11, RA4
AD19 RBA1
AD20 RDQ11
AD21 RDQM1
AD22 RDQ14
AD23 AVSS12_MEMPLL
AD24,
RDQ29_B, RDQ24_B
AD25
AD26 RDQM2_B
AD27 RODT_B
AD28 RRAS_B
AE1,
NFD7, NFD6
AE2
AE3 NFRBN
AE4 NFRBN2
AE5 GPIO6
AE6 GPIO5
AE7 TMS
AE8,
RDQ24, RDQ26
AE9
AE10 DVCC15_IO_1
AE11,
RDQ31, RDQ21
AE12
AE13 RWE_
AE14 DGND
AE15 RCS_
AE16 RA7
AE17 DVCC15_IO_1
AE18 RDQ2
AE19 RA1
AE20 DGND
AE21 RDQM0
AE22 RDQ12
AE23 AVDD12_MEMPLL
AE24 TP_MEMPLL
AE25 RDQ25_B
AE26 RDQM3_B
AE27 RA0_B
AE28 RWE_B_
AF1 to
NFD5, NFD4, NFD2
AF3
AF4 NFALE
AF5 SFCK
AF6 TDO
AF7 TRST_
AF8, AF9 RDQ25, RDQ27
AF10 DGND
I/O
- External reference resistor connection terminal
O Read enable signal output to the NAND fl ash
O Chip enable signal output terminal
O Jig mode selection signal output terminal
I Test clock signal input terminal (for JTAG)
I Test data input terminal (for JTAG)
O Data mask signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
O Address signal output to the SD-RAM
O Column address signal output to the SD-RAM
O Address signal output to the SD-RAM
O Bank address signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
O Data mask signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
- Ground terminal
I/O Two-way data bus with the SD-RAM
O Data mask signal output to the SD-RAM
O On die termination enable signal output to the SD-RAM
O Row address signal output to the SD-RAM
I/O Two-way data bus with the NAND fl ash
O Ready/busy selection signal output to the NAND fl ash
O Ready/busy selection signal output terminal
O Writing end fl ag signal output to the sub system controller
Jig mode selection signal input from the main system controller
I
"L": USB writing mode, "H": normal mode
I Test mode selection signal input terminal (for JTAG)
I/O Two-way data bus with the SD-RAM
- Power supply terminal (+1.5V)
I/O Two-way data bus with the SD-RAM
O Write enable signal output to the SD-RAM
- Ground terminal
O Chip select signal output to the SD-RAM
O Address signal output to the SD-RAM
- Power supply terminal (+1.5V)
I/O Two-way data bus with the SD-RAM
O Address signal output to the SD-RAM
- Ground terminal
O Data mask signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
- Power supply terminal (+1.2V)
- Test terminal
I/O Two-way data bus with the SD-RAM
O Data mask signal output to the SD-RAM
O Address signal output to the SD-RAM
O Write enable signal output to the SD-RAM
I/O Two-way data bus with the NAND fl ash
O Address latch enable signal output to the NAND fl ash
O Serial data transfer clock signal output terminal
O Test data output terminal (for JTAG)
I Test reset signal input terminal (for JTAG)
I/O Two-way data bus with the SD-RAM
- Ground terminal
Description
Not used
"L": busy, "H": ready
Not used
"H": end
Not used
STR-DA2800ES
161