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CHAPTER 5: Technical Description
5. Technical Description
The IC132C adapter uses the 16554 UART. This chip features programmable baud
rate, data format, interrupt control and a 16-byte input and output FIFO, and is
functionally (4) 16550 UARTs. The IC132C-HS uses the 16654 UART, which has
a 64-byte FIFO as opposed to the 16-byte FIFO available in the 16554. The
IC188C-R2 uses the 16854 UART, which has a 128-byte FIFO buffer.
5.1 Interrupts
A good analogy of a PC interrupt would be the phone ringing. The phone "bell" is
a request for us to stop what we are currently doing and take up another task
(speak to the person on the other end of the line). This is the same process the PC
uses to alert the CPU that a task must be performed. The CPU, upon receiving an
interrupt, makes a record of what the processor was doing at the time and stores
this information on the "stack"; this allows the processor to resume its predefined
duties after the interrupt is handled, exactly where it left off. Every main sub-system
in the PC has its own interrupt, frequently called an IRQ (short for Interrupt
ReQuest).
The ability to share IRQ is an important feature for any add-in I/O card. Consider
that in the IBM
®
XT™, the available IRQs were IRQ0 through IRQ7. Of these
interrupts, only IRQ 2–5 and IRQ 7 were actually available for use. This made the
IRQ a very valuable system resource. To make the maximum use of these system
resources, an IRQ-sharing circuit that allowed more than one port to use a selected
IRQ was devised. This worked fine as a hardware solution but presented the
software designer with a challenge to identify the source of the interrupt. The
software designer frequently used a technique referred to as "round robin polling."
This method required the interrupt service routine to "poll" or interrogate each
UART as to its interrupt pending status. This method of polling was sufficient for
use with slower-speed communications, but as modems increased their throughput
abilities, this method of servicing shared IRQs became inefficient.
5.2 Why Use an ISP?
The answer to the polling inefficiency was the Interrupt Status Port (ISP). The ISP
is a read-only 8-bit register that sets a corresponding bit when an interrupt is
pending. Port 1 interrupt line corresponds with Bit D0 of the status port, Port 2
with D1, etc. The use of this port means that the software designer now only has to
poll a single port to determine if an interrupt is pending.
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