Panasonic SV-MP500VGK Service Manual page 21

Solid State Audio
BLOCK DIAGRAM
ROM
32kB
SRAM
64kB
A12,A17,C9,E18,
D16,D18,A14,
MPMC
B14,A13,B13,
(Multi Purpose
A1,A2,B2,A3,
Memory Control)
A4,B4,A5,B5.
Fiash-Memory Control
Data,Command and
Address I/O
V15
Flash
U5,T6,U6,T7,
10-bits ADC
ADC10B
U7,V10,U10
AUDIO SS
U3,V3,T3,U2,
V1,V2,T1,T4, MIC/
U1,R3,T2. ADC
IC3 C2DBGL000001
Micro Processor Unit
(MPU)
Multi-Layer AHB
(AHB=Advanced High-Performance Bus)
ROMI
RAMI
AHB and
VPB Bridge
(ASYNC)
AHB and
VPB Bridge
(ASYNC)
FLASH
Interface
interface
M
SAI
DEC
U
X
SV-MP500VGK / SV-MP500VGH / SV-MP500VGC / SV-MP500VGD / SV-MP500VGN
C2DBGL000001
AHB and AHB and
VPB Bridge VPB Bridge
(ASYNC) (SYNC)
AHB and
MEM Bridge
(ASYNC)
USB 2.0 FS ATX
Interface
Master/Slave
IIC Interface
INTC MEM CNTR
Digital
Audio
Codec
SRC
SAO
21
G2,F2,E3,E2,
LCD
D3,D1,D2,C3,
Interface
C1,C2,B3,F3.
T15,U17,T17,
U14,P16,R17,
R16,T16,U15,
U16,U18,V18
H16,J17
M3,M2,L1,L2,
M M1,P3,N3,N2,
DAC
INT
U
N1,R1,R2,P2,
HP
X
P1.