Panasonic SV-MP500VGK Service Manual page 20

Digital audio player
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SV-MP500VGK / SV-MP500VGH / SV-MP500VGC / SV-MP500VGD / SV-MP500VGN
MAIN BLOCK
C
3V
IC7
DC-DC
1.2V
CONV
IC4
EL
DRIVER
ICP1
BATTERY
1.2V
IC10
Regulator
15
14
13
12
11
10
9
8
7
O
6
P
5
4
Q
3
R
2
S
1
CN1
(TO MEMORY CIRCUIT CN5)
Notes :
Radio Signal Line.
REC Signal Line.
MP3/FM/IC REC Signal Line.
CN2
(TO TUNER CIRCUIT CN6)
24
1
2
23
3
22
4
21
5
20
6
19
18
7
17
8
ADAPTOR
9
16
10
15
IN VCC 5V
11
14
12
13
ICP2
USB_VBUS:
USB Supply detection line
3.26V
usb 2.0 FS & usb 2.0
USB_DM:
Negative USB data line
usb 2.0 FS
USB_DP: Positive USB data line
usb 2.0 FS
3.26V
USB_RPU: Soft connect output usb 2.0 FS
T18
DC_DC_VUSB:USB supply voltage
L7
N17
DC_DC_LX2:
Connection to DC/DC2 external coil
0V
P17
DC_DC_LX1:
L10
Connection to DC/DC1 external coil
DC_DC_VBAT:
M17
Battery supply voltage
R18
DC/DC1 3.3V output voltage
DC/DC1 3.3V input voltage
M16
V10
Analog supply 10-bit ADC
A12 MPMC_BLOUT0:
The signals nMPMCBLSOUT[0]
select byte lane [7:0] on the data bus.
Used for static memories.
A17
MPMC_NOE:
Output enable for static memories.
Active LOW. Used for static
memory devices.
C9
MPMC_NSTCS_0:
Static memory chip select 0.
Default active LOW. Used
for static memory device.
E18
MPMC address 2
D16 MPMC address 3
MPMC address 5
D18
16
17
18
19
20
21
22
23
24
25
26
T
27
28
U
29
V
W
30
CN3
3.3V
USB PORT
Q6
USB
CONTROL
U14 T17
B3
C2
U17
T15
F3
LCD_RS: 'high' Data
register selsct 'low'
Instruction register select
LCD_CSB: Chip Select
LCD_E_RD: 6800 enable
LCD_RW-WR:
6800 read/write select 8080 active "high" write enable
HP_OUTCA: HEADPHONE common output reference
HP_OUTCB: HEADPHONE common output reference
IC3
C2DBGL000001
DSP IC
A14
B14
A13
A1 A2
B2
A3
A4 B4 A5 B5
U
V
W
3.3V
S
R
Q
Battery Chargeable Control Pin
SV-MP500V(GK)(GH)(GC)(GD)(GN) BLOCK DIAGRAM
20
VDD
15
LCD1 Display
C1 C3 D2 D1 D3 E2 E3 F2 G2
8080 active "high" write enable
ADC_VINR: SADC Right Analog Input
T1
ADC_VINL: SADC Left Analog Input
T4
ADC_MIC: Microphone Input
R3
HP_OUTR: SDAC Right Headphone Output
P3
N2
N1
HP_OUTL: SDAC Left Headphone Output N3
T10
XTALH_IN
12 MHz clock input
XATLL_OUT
V9
12 MHz clock input
G16
K2
T
430.0mV P-P
P
O
Q7
Battery
Chargeable
Control
Battery 1.2V
IC9
Reset
3.3V
12MHz
X2

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