CDX-GT61UMS/GT560UE/GT560UI/GT560US/GT564UI/GT610UG/GT610US/GT616UG
Pin No.
Pin Name
69
ADVDD3
70
ADIN1 (IN_L-CH)
71
ADVREFL
72
ADVCM
73
ADVREFH
74
ADIN2 (IN_R-CH)
75
ADVSS3
76
MS
77, 78
BUS0, BUS1
79
So
80
Si
81
SCL
82
/CCE
83
VDD3-2
84
VSS-3
85
/RST
86
VDD1-4
87
DEC_REQ
88
BSIF-REQ
89
BSIF-GATE
90
BSIF_DATA
91
BSIF_BCK
92
BSIF_LRCK
93
BSIF_XMUTE
94
ZDET
95
SP_DATA
96
SP_CLK
97
TEST
98
PDO
99
TMAX
100
LPFN
I/O
-
Power supply terminal (+3.1V)
I
Audio signal input terminal (L channel)
O
Reference voltage output terminal
O
Reference voltage output terminal
O
Reference voltage output terminal
I
Audio signal input terminal (R channel)
-
Ground terminal
I
I/F mode selection signal input terminal
I/O
Bus data input/output terminal
O
Serial data output to the CD drive/USB controller
I
Serial data input from the CD drive/USB controller
I
Bus clock signal input from the CD drive/USB controller
I
Chip enable signal input from the CD drive/USB controller
-
Power supply terminal (+3.1V)
-
Ground terminal
I
Reset signal input from the system controller
-
Power supply terminal (+1.5V)
O
Request signal output to the CD drive/USB controller
O
Request signal output to the CD drive/USB controller
I
Gate signal input from the CD drive/USB controller
I
Audio data input from the CD drive/USB controller
I
Bit clock signal input from the CD drive/USB controller
I
L/R sampling clock signal (44.1 kHz) input terminal for audio data input
I
Muting on/off control signal input from the CD drive/USB controller
O
Zero detection signal output terminal
O
Spectrum analyzer data output to the system controller
I
Spectrum analyzer data transfer clock signal input from the system controller
I
Setting terminal for test mode
O
Phase error margin signal between EFM signal and PLCK signal output terminal
O
TMAX detection result output terminal\
I
Inverted signal input from the operation amplifi er for PLL loop fi lter
Description
Fixed at "L" in this unit
Not used
Normally fi xed at "L"
39