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IC701 (CXD3030R) : DSP
Generates Error Signal and return to the Servo by the Signal from RF Amplifier IC.
Block Diagram
138
MCKO
70
V16M
94
VCKI
102
FSTIO
84
C4M
85
86
C16M
VCTL
41
VCOI
79
PCO
44
FILI
43
FILO
42
CLTV
45
47
RFAC
*
49
ASYI
50
ASYO
ASYE
81
WFCK
27
SCOR
60
GRSCOR
10
EXCK
77
SBSO
91
SQCK
62
SQSO
61
MDS
103
MDP
12
MON
93
FSW
100
Shaper
13
PWMI
SIGNAL PROCESSOR BLOCK
TEST
95
TEST2
104
TEST3
103
XRST
21
ADIO
33
RFDC
34
CE
35
TE
36
SE
37
FE
38
VC
39
82
139 40
Clock
32K RAM
Generator
OSC
Digital PLL
Vari-Pitch
double
EFM
speed
Demodulator
Sync
MUX
protector
Timing
Generator1
Subcode
P~W
processor
Subcode Q
processor
CLV
processor
18~times
Noise
oversampling
filter
MIRR
SERVO BLOCK
DFCT
FOK
O
Amp
p
A/D
CONVERTER
AnaSw
75 76 74
Address
generator
Priority
encoder
8
D/A
data
processor
Error
corrector
Error Rate
Counter
Digital Out
Timing
CPU
Generator2
interface
Servo
auto
sequencer
Servo
Interface
SERVO DSP
FOCUS SERVO
TRACKINGSERVO
SLED SERVO
* :
Asymmetry
Correction
96
80 8 9
DAC BLOCK
8Fs Digital Filter
+
1 bit DAC
Peak
detector
DAC
O
Amp
p
FOCUS
TRACKING
SLED
5
PWM1P
142
PWM1N
143
PWM2P
135
PWM2N
134
PSSL
111
PCMD48
116
BCK48
118
LRCK48
113
PCMD64
89
BCK64
88
LRCK64
87
GTOP. XUGF. XPLCK
121, 123, 25, 59
GFS. RFCK. C2PO. XRAOF
28, 126, 128
MNT0~3
16~19
MUTE
65
DOUT
10
83
MD2
DATA
97
CLOK
98
99
XLAT
SENS
63
COUT
58
MIRR
57
DFCT
14
FOK
56
FAO
4
TAO
3
SAO
2
37
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