Broadcom PLX PCI 9052RDK-LITE Hardware Reference Manual
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Broadcom PLX PCI 9052RDK-LITE Hardware Reference Manual

Broadcom PLX PCI 9052RDK-LITE Hardware Reference Manual

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Summary of Contents for Broadcom PLX PCI 9052RDK-LITE

  • Page 1 PCI 9052RDK-LITE Hardware Reference Manual...
  • Page 3 PCI 9052RDK-LITE Hardware Reference Manual Version 1.3 October 2004 Website: http://www.plxtech.com http://www.plxtech.com/support/ Technical Support: Phone: 408 774-9060 800 759-3735 Fax: 408 774-2169...
  • Page 4 © 2004 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
  • Page 5 BOUT ANUAL This document describes the PLX PCI 9052RDK-LITE, a Rapid Development Kit, from a hardware perspective. It contains a description of all major functional circuit blocks on the board and also is a reference for the creation of software for this product. This manual also includes complete schematics and bill of materials.

  • Page 7: Table Of Contents

    ABLE OF ONTENTS 1. GENERAL INFORMATION....................1 1.1 F ............................2 EATURES 1.2 RDK I .......................... 2 NSTALLATION 2. PCI 9052 OVERVIEW ......................3 2.1 PCI 9052 I ......................... 3 NTRODUCTION 2.2 PCI 9052 F ........................3 EATURE 3. RDK HARDWARE ARCHITECTURE ...................5 3.1 A .......................
  • Page 8 IST OF IGURES Figure 1-1. PCI 9052RDK-LITE Layout Diagram .................. 1 Figure 3-1. PCI 9052RDK-LITE Hardware Block Diagram ..............5 Figure 3-2. BGA to PGA Conversion ....................12 IST OF ABLES Table 3-1. PCI 9052RDK-LITE Default Memory Map ................6 Table 3-2.

  • Page 9: General Information

    1. General Information ISA Connector 16 pin 16 pin 16 pin SOIC SOIC SOIC OS C 176/100/48 20 pin 20 pin PQFP SOIC SOIC 24 pin SSOP 25x25 0.1" through hole FP1 for flash memory proto typing area SRAM 20 pin 20 pin 24 pin SOIC...

  • Page 10: Features

    Features The PCI 9052RDK-LITE Rapid Development Kit (RDK-LITE) board is a versatile PCI bus target development platform. It contains a 12.28” L x 5.20” W, four-layer, assembled PC board with the following features: • PLX PCI 9052 PCI Target interface chip with direct ISA interface •...

  • Page 11: Pci 9052 Overview

    2. PCI 9052 Overview PCI 9052 Introduction The PLX PCI 9052 provides a compact, high-performance PCI bus target (slave) interface for adapter boards. It is designed to connect a wide variety of local bus designs to the PCI bus and allow them to achieve high data rate burst transfers on the PCI bus.
  • Page 12 • Read/write strobe delay and write cycle hold. Read and Write (RD# and WR#) signals can be delayed from the beginning of a local bus cycle to allow the local bus timing to be tailored to the requirements of specific peripherals. The Write Cycle Hold option extends the data valid time for additional clock cycles beyond WR# strobe de-assertion.

  • Page 13: Rdk Hardware Architecture

    3. RDK Hardware Architecture Architecture Overview A block diagram of the PCI 9052RDK-LITE board is shown in Figure 3-1. The board is designed to support the product development of 32-bit, 33 MHz PCI target adapters. It features a PLX PCI 9052 device that interfaces user logic to a 32-bit, 33 MHz PCI bus.

  • Page 14: Hardware Memory Map

    Hardware Memory Map Table 3-1. PCI 9052RDK-LITE Default Memory Map Address Range Device Chip Select Comments 0FFF FFFF Unused Unused Unused 0300 0000 020F FFFF ROM Socket CS3# 0200 0000 0101 FFFF SRAM CS2# 0100 0000 In ISA mode the 000F FFFF ISA Memory space CS0# &...

  • Page 15: Table 3-2. Serial Eeprom Contents

    Table 3-2. Serial EEPROM Contents Serial Register Bits Register Register Register Description Register Value Description EEPROM Affected Values Offset Offset PCI 02h Device ID PCIIDR [31:16] 5201 Device ID for PCI 9052RDK-LITE PCI 00h Vendor ID PCIIDR [15:0] 10B5 PLX Vendor ID PCI 0Ah Class Code PCICCR [23:8]...
  • Page 16 Serial Register Bits Register Register Register Description Register Value Description EEPROM Affected Values Offset Offset MSW of Bus Region Descriptors for Local 2Ah LAS0BRD [31:16] 0040 Local Address Space 0 Sets bus width to 16 for ISA Memory space accesses. No prefetching. LSW of Bus Region Descriptors for Local 28h LAS0BRD [15:0]...

  • Page 17: Local Bus Operating Modes

    Local Bus Operating Modes The PCI 9052 local bus can be programmed to operate in 8- or 16-bit ISA bus mode, 8-,16-, or 32-bit non-multiplexed address/data bus mode (C-Mode) or 8-, 16-, or 32-bit multiplexed address/data bus (J- Mode). Programming of the PCI 9052 local bus operation is controlled by the value on the device’s MODE pins and INTCSR[12] during power-up.

  • Page 18: Test Headers

    The ROM can also be accessed by a local bus master by driving the XCSROM# signal on the CPLD (prototyping pad PC7) in conjunction with the local bus address, data, control and bus arbitration signals. Note: When a 3.3V device is used in the ROM socket, please make sure it has 5V-tolerant I/O. Test Headers Six logic analyzer headers are implemented with the standard 0.1”, 2x10 Hewlett Packard configuration.

  • Page 19: Prototyping Area

    Prototyping Area The RDK board contains a large prototyping area that contains 28 surface mount footprints, one 0.05” pitch BGA landscape, a 25x25 0.1” grid through-hole prototyping area and 5 power rails. Table 3-3. PCI 9052RDK-LITE Board Prototyping Area Footprints Package Qty.

  • Page 20: Bga Prototyping

    3.9.1 BGA Prototyping This RDK features a 26x26 @ 0.05” pitch BGA landscape with a plated-hole size of 0.022” diameter +/- 0.001”. Users can prototype with BGA devices by using BGA to PGA adapters. Referring to Figure 3-2, designers can use one of two methods to prototype with BGA devices. Both methods require soldering the BGA device to a BGA Land Socket.
  • Page 21 Table 3-4. Configuration Jumper Settings Function Option Jumper Jumper Jumper Location Setting Default Local Bus Operation Non-Multiplexed Multiplexed Local Interrupt 1 (LINTi1) Termination LINTi1 Active High LINTi1 Active Low Local Interrupt 2 (LINTi2) Termination LINTi2 Active High LINTi2 Active Low Local Interrupt 1 (LINTi1) Routing ISA_INT to LINTi1 9-10...

  • Page 23: Isa To Pci Migration

    4. ISA to PCI Migration This chapter explains how to use the PCI 9052RDK-LITE to migrate ISA bus designs to PCI bus designs. ISA Register Configuration The PCI 9052 uses a re-mapping process to map an ISA card into PCI space. Local address spaces 0 and 1 are used for memory accesses and I/O space accesses, respectively.

  • Page 24: Isa Register Configuration Example

    ISA Register Configuration Example Assume that the ISA card requires 1K bytes of memory space starting at address 0x1000h on the ISA bus and 16 bytes of I/O space starting at address 0x308h. 4.2.1 ISA Memory Mapping Starting with the memory space first, LAS0RR must be set to the inverse of the 1K bytes. 1K is 0x3ffh (if location 0 is included), the inverse is 0xfffffc00h and this is the number to be placed into LAS0RR.

  • Page 25: Initialization Control Register

    4.2.4.2 Initialization Control Register The Initialization Control Register CNTRL must be set to 0x007X0X12h where X represents the appropriate values for the specific adapter. For PCI v2.1 compatible systems, set CNTRL[18] = 0 and CNTRL[14] = 1, in which case CNTRL[22:19] become Don’t Cares. 4.2.4.3 Interrupt Control/Status Register The Interrupt Control/Status Register bit (INTCSR[12]) must be set to 1 to enable ISA interface mode.

  • Page 26: Isa Nows# Delay Option

    address was not a multiple of the range. The I/O region for the ISA device was from 0x308h to 0x317h. To write to the first I/O location in the ISA card, care has to be taken. An access to location 0x0000fc08h will map to location 0x308h on the local bus.
  • Page 27 Drive AEN (on the ISA connector) using the Chip Select CS3# output, and program the CS3BASE register value in EEPROM, to assert the Chip Select for the ISA address range(s). Since CS3# and USER3 signals are multiplexed onto the same pin 141, with USER3 being the PCI 9052 default configuration, CS3# functionality must be enabled by setting the CNTRL[9] bit value in EEPROM to 1.

  • Page 28: Customer Support & References

    Prior to contacting customer support, please ensure you are sitting close to the computer that has the PCI 9052RDK-LITE and have the following information: 1. Serial Number of the PLX PCI 9052RDK-LITE 2. Operating System and type 3. Description of problem You may contact PLX Technology, Inc.

  • Page 29: Bill Of Materials / Pld & Circuit Schematics

    6. Bill of Materials / PLD & Circuit Schematics The following pages contain the Bill of Materials, the PLD Schematics and the Schematics for the PCI 9052RDK-LITE circuit board. Table 6-1. Bill of Materials Item# Mfg Part Number Description Package Source Part Reference Surface mount components...
  • Page 30 Item# Mfg Part Number Description Package Source Part Reference Alliance AS7C256-15JC SRAM, 32Kx8 SOJ-28 pin U7, U10, U15, U16 Samtec ICF-308-T-O 8-pin socket, 300mil 90-0023-001-A PCB, PCI9052RDK-LITE (Use schematic 91-0023-002-A r002) Through hole components Aries Electronis 1108800 half size Thru hole Digi-key socket Harwin...
  • Page 31 ECN HISTORY ECN NUMBER DATE NOTE 1/11/2000 Started the project 18/04/2001 First Production 7/08/2002 Update RN20, RN21, RN22 from 10K to 1K on sheet 4 to reflect the BOM Update U6 from 93CS46L to 93LC46B to reflect the BOM Update the BOM and schematic document number Changed LRESET# to LRESET for ISA interface Mode PCI9052RDK-LITE BLOCK DIAGRAM...
  • Page 32 AD[31:0] -12V -12V AD[31:0] C/BE3L PCI Card Edge Connector C/BE3L PCLK PCLK C/BE1L C/BE1L SERRL SERRL PERRL PERRL -12V LOCKL +12V LOCKL -12V -12V TRST# DEVSELL +12V DEVSELL +12V AD10 IRDYL PCI_TDD PCI_TDD AD11 IRDYL AD12 C/BE2L INTAL AD13 C/BE2L INTA# AD14 0.01uF...
  • Page 33 BLAST# USER0/WAITo# LBE0# CS0# AD[31:0] LA[27:2] LBE1# ADS# CS1# LW/R# AD[31:0] LA[27:2] USER1/LLOCKo# LBE2# LHOLD READY# LBE3# BTERM# USER2/CS2# 742-08-3-103-J-XX 742-08-3-103-J-XX 742-08-3-103-J-XX 742-08-3-103-J-XX USER3/CS3# CHRDY LA10 LA14 LA11 LA15 LA10 LA12 LA16 LA10 LA11 LA13 LA17 LA11 AD10 LA12 AD10 LA12 AD11 LA13...
  • Page 34 SRAM CS# Configuration. LA[27:2] Fit links to choose LA[27:2] LA[27:2] LD[31:0] LA[27:2] LD[31:0] LA[27:2] LD[31:0] LA[27:2] LD[31:0] LD[31:0] appropriate CS# for LD[31:0] SRAM and ROM LD16 LD24 I/O0 I/O0 I/O0 I/O0 LD17 LD25 I/O1 I/O1 I/O1 I/O1 LD10 LD18 LD26 CS0# I/O2 I/O2...
  • Page 35 Local Address Bus -Upper Addresses Test Headers LA[27:2] LA[27:2] Note: these are designed to hook up directly to HP logic analyzer termination adapter 01650-63203. LAH1 CLK2 LA27 LA27 CLK1 PD16 LA26 LA26 LA25 LA25 PD15 LA24 LA24 LA23 LA23 PD14 LA22 LA22 LA21...
  • Page 36 Note: Place four PLCC devices co-incident on the component Prototyping Footprint A side of the board; that is, they share common pins and the 28 fits inside the 44 which fits inside the 68 which fits inside the All prototyping Footprints are located on the component side of the PCB PE12 PE74...
  • Page 37 Prototyping Footprint B All prototyping footprints are located on the component side of the PCB. FP15 FP16 FP17 FP18 PG33 PG52 PG53 PG72 PG16 PG17 PG32 PG34 PG51 PG54 PG71 PG15 PG18 PG31 PG35 PG50 PG55 PG70 PG14 PG19 PG30 PG36 PG49 PG56...
  • Page 38 Prototyping Footprint C FP28 FP29 PH156 PH155 PH148 PH154 PH10 PH147 PH153 PH11 PH146 PH152 PH12 PH145 PH151 PH13 PH144 PH150 PH14 PH143 PH149 PH15 PH142 PH148 PH16 PH141 PH10 PH147 PH17 PH140 PH11 PH146 PH18 PH139 PH12 PH145 PH19 PH138 PH13 PH144...
  • Page 39 Prototyping Footprint D All prototyping footprints are located on the component side of the PCB. FP31 PI132 PI131 FP32 PI130 PI129 PI128 PI10 PI123 PI127 PI11 PI122 PI126 PI12 PI121 PI125 PI13 PI120 PI124 PI14 PI119 PI10 PI123 PI15 PI118 PI11 PI122 PI16...

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