Sony ICD-SX700 Service Manual page 38

ICD-SX700/SX700D/SX800/SX800D/SX900
Pin No. Pin Name
P23 LCD_PXCLK
P24 ID
P25 I/O_A
P26 I/O_A
R1 SDR_DATA0
R2 SDR_DQM3
R3 SDR_DQM2
R4 SDR_DQM1
R5 SDR_WEZ
R8 SDR_DATA1
R9 GND
R10 MWI_SI
R17 U70_CTSZ
R18 U70_RTSZ
R19 GND
R22 LCD_R2
R23 LCD_R4
R24 GNDSINK
R25 VDD_L0
R26 NC
T1 SDR_CKE0
T2 SDR_CSZ1
T3 SDR_CSZ0
T4 SDR_BA1
T5 SDR_RASZ
T8 SDR_CKE1
T9 GND
T10 MWI_SO
T17 U70_SOUT
T18 U70_SRIN
T19 GND
T22 LCD_R5
T23 NC
T24 C_TMS
T25 VLOG
T26 CKO
U1 SDR_A12
U2 SDR_A11
U3 SDR_A10
U4 SDR_A9
U5 SDR_A8
U8 SDR_CASZ
U9 GND
U10 MWI_CS0
U11 MWI_SK
U12 GI/O_P1
U13 GI/O_P0
U14 L0_DET
U15 L1_DET
U16 ERR_RST_REQZ
U17 CK32KI
U18 REFCLKO
U19 D_TCK
U22 C_TDO
U23 VLOGIN
U24 C_TCK
38
I/O
O Pixel clock (Not used (Open))
— Not used (Open)
— Power supply to I/OA
— Power supply to I/OA
I/O Read/write data
O Write data mask (Not used (Open))
O Write data mask (Not used (Open))
O Write data mask
O Write enable signal (Low active)
I/O Read/write data
— GND
I Data input (Not used (Open))
I connection/On destination/On device data send/receive ready (Low active) (Not used (Open))
O Data send/receive ready (Low active) (Not used (Open))
— GND
O R data (Not used (Open))
O R data (Not used (Open))
— GND
— Power supply to the logic block 0
— Not used (Open)
O Clock enable signal
O Chip select signal (Low active) (Not used (Open))
O Chip select signal (Low active)
O Bank address
O RAS signal (Low active)
O Clock enable signal (Not used (Open))
— GND
O Data output (Not used (Open))
O Serial data output
I Serial data input
— GND
O R data (Not used (Open))
— Not used (Open)
I CPU debugger connection/On terminal
O REGLOG power output terminal (1.86V)
O Crystal connection/On terminal
O SDR address output
O SDR address output
O SDR address output
O SDR address output
O SDR address output
O CAS signal (Low active)
— GND
O Chip select 0 (Not used (Open))
O Clock output (Not used (Open))
I/O General purpose input/output terminal 1 (Not used (Open))
I/O General purpose input/output terminal 0 (Not used (Open))
I Voltage monitor/reset of logic 0 block (Not used (Open))
I Voltage monitor of logic 1 block
O Not used (Open)
I Reference clock input 32.768 kHz (Not used (Open))
O Reference clock output
O Input/output and interrupt input to general purpose I/O
O CPU debugger connection/On terminal
I REGLOG power input terminal
I CPU debugger connection/On terminal
Description