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Rockwell RFX144V24-S23 Designer's Manual

Monofax modems
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Designer's Guide
(Preliminary)
Order No. 1070
February 14, 1996

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  • Page 1 Designer's Guide (Preliminary) Order No. 1070 February 14, 1996...
  • Page 2 Information furnished by Rockwell International Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Rockwell International for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Rockwell International other than for circuitry embodied in Rockwell products.

  • Page 3: Table Of Contents

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table of Contents 1. INTRODUCTION ............................. 1-1 1.1 SUMMARY ..............................1-1 1.2 FEATURES..............................1-3 1.3 TECHNICAL SPECIFICATIONS ......................... 1-5 2. HARDWARE INTERFACE SIGNALS ......................2-1 3. SOFTWARE INTERFACE ..........................3-1 3.1 INTERFACE MEMORY ..........................3-1 3.1.1 Interface Memory Map ........................
  • Page 4 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 7. DTMF DIALING WITH AUTO DIALER ......................7-1 7.1 DTMF REQUIREMENTS..........................7-1 7.2 SETTING OSCILLATOR PARAMETERS....................7-1 7.3 DETECTING ANSWER TONE........................7-2 7.4 COMPLETE CALLING SEQUENCE ......................7-2 7.5 SINGLE TONE GENERATION ........................7-4 8.
  • Page 5 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 12.3.3 Tone Transmit Mode ........................12-3 12.3.4 Handset Mode ..........................12-3 12.3.5 Microphone Volume Control......................12-4 12.3.6 Speaker Volume Control....................... 12-4 12.3.7 Microphone and Speaker Muting ....................12-5 12.3.8 Microphone and Speaker AGC ..................... 12-5 12.3.9 Speech Detectors .........................
  • Page 6 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide List of Figures Figure 2-1. Modem Functional Interconnect Diagram......................2-2 Figure 2-2. MDP Pin Signals - 100-Pin PQFP ........................2-3 Figure 2-3. XIA Pin Signals - 28-Pin PLCC ........................2-5 Figure 2-4. Microprocessor Interface Waveforms ......................2-15 Figure 2-5.
  • Page 7 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Figure 9-25. PPS and PPR Frame Structure........................9-28 Figure 9-26. Signal Recognition Algorithm in High Speed Mode ..................9-30 Figure 9-27. FSK Signal Detection Algorithm in Voice Mode .................... 9-31 Figure 9-28. CNG Detection (1100 Hz) in Voice Mode ..................... 9-32 Figure 9-29.
  • Page 8 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide List of Tables Table 1-1. Modem Models and Supported Features ......................1-2 Table 1-2. Configurations, Signaling Rates, and Data Rates ....................1-6 Table 1-3. Turn-On Sequence Times..........................1-7 Table 1-4. Turn-Off Sequence Times..........................1-7 Table 1-5.

  • Page 9: Introduction

    1. INTRODUCTION 1.1 SUMMARY The Rockwell RFX144V24-S23 and RFX96V24-S23 MONOFAX ® facsimile modem family provides 14400 bps and 9600 bps half-duplex capability with options supporting DigiTalk™ voice and ADPCM audio codecs, DigiTalk™ full-duplex speakerphone, and V.23 full-duplex. The modem models are identified in Table 1-1.

  • Page 10: Table 1-1. Modem Models And Supported Features

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 1-1. Modem Models and Supported Features Package(s) Supported Features DigiTalk Voice and Full-Duplex Full-Duplex Maximum ADPCM Audio Codecs Speakerphone V.23 Modem Model (100-Pin PQFP) (28-Pin PLCC) Line Speed (V24) (-S) (-23) RFX144V24-S23 14.4 kbps •...

  • Page 11: Features

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 1.2 FEATURES • Group 3 facsimile transmission/reception ITU-T V.17 and V.33 (RFX144 models) ITU-T V.29, V.27 ter, T.30, V.21 Channel 2, T.4 HDLC framing at all speeds Receive dynamic range: 0 dBm to -43 dBm...
  • Page 12 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide • 2-wire V.23 (-23 Option) Full-duplex modes: TX = 75 bps, RX = 1200 bps TX = 1200 bps, RX = 75 bps Half-duplex mode: TX = RX = 1200 bps Serial and parallel data modes...

  • Page 13: Technical Specifications

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 1.3 TECHNICAL SPECIFICATIONS Configurations, Signaling Rates and Data Rates The selectable modem configurations, along with the corresponding signaling (baud) rates and data rates, are listed in Table 1-2. Tone Generation The modem can generate voice-band single or dual tones from 0 Hz to 4800 Hz with a resolution of 0.15 Hz and an accuracy of 0.01%.

  • Page 14: Table 1-2. Configurations, Signaling Rates, And Data Rates

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Receive Dynamic Range The receiver satisfies PSTN performance requirements for received line signal levels from 0 dBm to -43 dBm measured at the Receiver Analog Input (RXA) input. An external input buffer and filter must be supplied between RXA and RIN.

  • Page 15: Table 1-3. Turn-On Sequence Times

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 1-3. Turn-On Sequence Times ~RTS On to ~CTS On Configuration Echo Protector Tone Disabled Echo Protector Tone Enabled V.17/V.33 1395 ms 1602 ms V.17 Short Train 144 ms 351 ms V.29 Long Train...

  • Page 16: Table 1-5. V.23 Default Turn-On And Turn-Off Sequences

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Voice Codec Mode (V24 Option) In this mode, the modem can compress a voice message at an average rate of 2.9 kbps or at a fixed rate of 4.7 kbps and decompress a voice message at various pitch synchronized playback speeds. Optional error correction coding is available for use with ARAMs.

  • Page 17: Hardware Interface Signals

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 2. HARDWARE INTERFACE SIGNALS The hardware interface signals are shown in Figure 2-1. In Figure 2-1, any point that is active when exhibiting the relatively more negative voltage of a two-voltage system (e.g., 0 VDC for TTL or -12 VDC for EIA/TIA-232-E) is called active low and is represented by a small circle at the signal point.

  • Page 18: Figure 2-1. Modem Functional Interconnect Diagram

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide XTLI XTLO CRYSTAL ~TALK RINGD DCLK TELEPHONE TELEPHONE USRT LINE LINE (OPTIONAL) ~RTS INTERFACE ~CTS TXA1 ~RLSD TXA2 SPKR ANALOG SWITCH RFX144V24-S23 ~READ SR4IN RXDAT MICOUT ~WRITE RFX96V24-S23 SPEAKER/ SR3OUT TXDAT TXA1 MONOFAX MICROPHONE...

  • Page 19: Figure 2-2. Mdp Pin Signals - 100-Pin Pqfp

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 1070F2-2 Pin Sigs 100F Figure 2-2. MDP Pin Signals - 100-Pin PQFP 1070...

  • Page 20: Table 2-1. Mdp Pin Signals - 100-Pin Pqfp

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 2-1. MDP Pin Signals - 100-Pin PQFP Signal Label I/O Type Interface Signal Label I/O Type Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface ~READ Host Parallel Interface...

  • Page 21: Figure 2-3. Xia Pin Signals - 28-Pin Plcc

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 1070F2-3 Pin Sigs 28L Figure 2-3. XIA Pin Signals - 28-Pin PLCC Table 2-2. XIA Pin Signals - 28-Pin PLCC Signal Label I/O Type Interface Signal Label I/O Type Interface DGND AGND A0VT AGND...

  • Page 22: Table 2-3. Mdp Hardware Interface Signal Definitions

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 2-3. MDP Hardware Interface Signal Definitions Label I/O Type Signal/Definition OVERHEAD SIGNALS XTLI, XTLO R, R Crystal In and Crystal Out. The modem must be connected to an external crystal circuit consisting of a third overtone 49.92 MHz or 53.76 MHz crystal, three capacitors, an inductor, and a resistor.
  • Page 23 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 2-3. MDP Hardware Interface Signal Definitions (Cont’d) Label I/O Type Signal/Definition ~READ–ø2 Read Enable–ø2. When ~EN85 is low (8085 bus selected), reading is controlled by the host pulsing ~READ input low during the microprocessor bus access cycle. The read timing is:...
  • Page 24 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 2-3. MDP Hardware Interface Signal Definitions (Cont'd) Label I/O Type Signal Name/Description V.24 SERIAL INTERFACE These pins provide timing, data, and control signals for implementing a ITU-T Recommendation V.24 compatible serial interface. These signals are TTL compatible in order to drive the short wire lengths and circuits normally found within stand-alone modem enclosures or equipment cabinets.
  • Page 25 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 2-3. MDP Hardware Interface Signal Definitions (Cont'd) Label I/O Type Signal Name/Description TELEPHONE LINE INTERFACE TXA1, TXA2 O(DF) Transmit Analog 1 and 2. The TXA1 and TXA2 outputs are differential outputs 180 degrees out of phase with each other.
  • Page 26 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 2-3. MDP Hardware Interface Signal Definitions (Cont'd) Label I/O Type Signal Name/Description EYE DIAGNOSTIC INTERFACE Three signals provide the timing and data necessary to create an oscilloscope quadrature eye pattern. The eye pattern is simply a display of the received baseband constellation. By observing this constellation, common line disturbances can usually be identified.

  • Page 27: Table 2-4. Xia Hardware Interface Signal Definitions

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 2-4. XIA Hardware Interface Signal Definitions Label I/O Type Signal Name/Description OVERHEAD SIGNALS P5VD, P5VT, Supply Voltage. Connect to VCC through a power decoupling filter. P5VR DGND, A0VT, Ground. Connect to analog ground.

  • Page 28: Table 2-5. Digital Electrical Characteristics

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 2-5. Digital Electrical Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Input High Voltage Type IA and IB – Type IC and ID 0.8 V – Input High Current µA VCC = 5.25 V, V IN = 5.25 V Type IB –...

  • Page 29: Table 2-6. Analog Electrical Characteristics

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 2-6. Analog Electrical Characteristics Name Type Characteristic Value > 70K Ω I (DA) Input Impedance Maximum AC Input Voltage 1.7 VP-P Reference Voltage* +2.5 VDC 300 Ω TXA1, TXA2 O (DD) Minimum Load Maximum Capacitive Load 0.01 µF...

  • Page 30: Table 2-7. Current And Power Requirements

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 2-7. Current and Power Requirements Current (ID) Power (PD) Typical Maximum Maximum Typical Maximum Maximum @ 25° @ 0°C @ -40°C @ 25°C @ 0°C @ -40°C Mode (mA) (mA) (mA) (mW) (mW)

  • Page 31: Figure 2-4. Microprocessor Interface Waveforms

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide READ WRITE RS0-RS4 ~WRITE READ TWDS TDHW TDHR D0-D7 a. 8085 Bus Compatible (EN85 = L) READ WRITE R0-RS4 R/~W TP2CH TWDS TDHR TDHW D0-D7 b. 6500 Bus Compatible (EN85 = H) 1070F2-4 MP WF Figure 2-4.

  • Page 32: Figure 2-5. Transmitter Signal Timing

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 2-9. Microprocessor Interface Timing Parameter Symbol Min. Max. Units ~CS Setup Time RSi Setup Time Data Access Time Data Hold Time TDHR Control Hold Time Write Data Setup Time TWDS Write Data Hold Time TDHW Phase 2 (ø2) Clock High...

  • Page 33: Figure 2-7. Eye Pattern Timing

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide EYESYNC 16 17 13 14 16 17 EYECLK EYEXY ~ EYECLK LRCLK 1070F2-7 EP Timing Figure 2-7. Eye Pattern Timing 1070 2-17...

  • Page 34: Figure 2-8. Eye Pattern Circuit

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide EYEXY P2-4 EYESYNC P2-3 ~EYECLK P2-2 9.12 CLK 1,2 CLR1 CLR2 74HC161 74HC161 74HC107 4.11 K1,K2 J1,J2 LOAD LOAD CLK SI CLK1 CLR2 CLR1 CLK2 74HC107 LRSEL 0.1u DGND J1,J2 10 13 4/8 fsel LRCLK 4.11...

  • Page 35: Software Interface

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 3. SOFTWARE INTERFACE Modem functions are implemented in firmware executing in the MDP DSP. 3.1 INTERFACE MEMORY The DSP communicates with the host processor by means of a dual-port, interface memory. The interface memory in the DSP contains thirty-two 8-bit registers, labeled register 00 through 1F (Figure 3-1).

  • Page 36: Figure 3-1. Interface Memory Map

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Register Reg. Function Addr. Default Interrupt Handling — — PIREQ — — SETUP XX0-XX0 B2IA B1IA B2I1E B2I2E B1I1E B1I2E --00-00- High Speed Control & Status SHPR* ASPEED* PRDET* — — — — 0000XXXX...

  • Page 37: Table 3-1. Interface Memory Bit Definitions

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions Mnemonic Location Default Name/Description 12TH 08:4 Select 12th Order. When control bit 12TH is a 1, the tone detectors operate as one 12th order filter (uses FR3).When 12TH is a 0, the tone detectors operate as three parallel independent 4th order filters (FR1, FR2, FR3).The 12th bit is valid in all reception modes except speakerphone and V.23.
  • Page 38 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description AREX1 05:6 RAM Access 1 Code Extension Select. When control bit AREX1 is a 1, the upper part (80h-FFh) of the RAM is selected. When AREX1 is a 0, the lower part (0-7Fh) is selected.
  • Page 39 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description B2I2E 1E:4 Buffer 2 Interrupt 2 Enable. When control bit B2I2E is a 1, ~IRQ2 is enabled for Buffer 2, i.e., the modem will assert ~IRQ2 when B2A is set to a 1 by the modem. When B2I2E is a 0, B2A has no effect on ~IRQ2.
  • Page 40 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description CONF 06:0-7 Configuration. The CONF control bits select one of the following configurations: CONF (Hex) Configuration V.17/V.33 14400 bps. (RFX144.)* V.17/V.33 12000 bps. (RFX144.)* V.17 9600 bps.
  • Page 41 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description Configuration Definitions: (Cont'd) V.17. The modem operates as specified in ITU-T Recommendation V.17. V.33. The modem operates as specified in ITU-T Recommendation V.33.
  • Page 42 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description 05:0 Coefficient RAM 1 Select. When control bit CR1 is a 1, AREX1 and ADD1 address Coefficient RAM. When CR1 is a 0, AREX1 and ADD1 address Data RAM. This bit must be set according to the desired RAM address (Table 4-1).
  • Page 43 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description DTDET 1C:6 – Dual Tone Detected. When configured as an DTMF receiver, the modem sets status bit DTDET to a 1 when a signal is received that satisfies all DTMF criteria except on-time, off-time, and cycle-time. The encoded DTMF Output Word (1C:0-3) value is available when DTDET is a 1.
  • Page 44 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description 09:2 – End of Frame. In HDLC mode, when the modem is configured as a transmitter and bit AEOF is a 0, the EOF bit is a control bit.
  • Page 45 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description 08:5 – Frequency No. 1. The modem sets status bit FR1 to a 1 when energy above tone detector 1's turn-on threshold is detected. The default detection range = 2100 Hz ± 25 Hz for 9600 Hz sample rate. The FR1...
  • Page 46 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description ITADRS 0A:0-4 Interrupt Address. These 5 bits specify the register upon which the programmable interrupt and ITBMSK will take effect. The address of the byte on which the modem asserts ~IRQ1 on a bit or bits in...
  • Page 47 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description 1C:5 – On-Time Satisfied. When configured as an DTMF receiver, the modem sets status bit OTS to 1 after the DTMF on-time criteria is satisfied. This bit is reset by the modem after DTMFD is set to a 1 or if the received signal fails to satisfy the DTMF off-time criteria.
  • Page 48 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description 07:5 Parallel Data Mode. When control bit PDM is a 1, parallel data mode is selected. If the modem is a transmitter, data for transmission is accepted from DBUFF (10:0-7) in modes other than V.23 or TBUFFER (12:0-7) in V.23 mode (CONF = 24).
  • Page 49 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description PRDET 1D:4 – Rate Sequence Detection. When status bit PRDET is a 1, the modem receiver has detected a rate sequence pattern containing a proper synchronization bit pattern. (V.17 or V.33 modes.) 1A:0 Relay A Active.
  • Page 50 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description SCR1 0C:4 – Scrambled Ones. When the modem is configured as a high speed transmitter, status bit SCR1 = 1 indicates scrambled ones are being sent. When SCR1 = 0, scrambled ones are not being sent.
  • Page 51 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description TTONEE 0E:7 Tone Transmit Enable. In speakerphone mode, control bit TTONEE enables (TTONEE = 1) or disables (TTONEE = 0) tone transmit mode. Depending upon the status of TONEIE and TONEXE, the corresponding voice channel will be muted for the whole period of the tone transmit mode.
  • Page 52 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description WDSZ 14:0,1 Data Word Size (Parallel Mode). In V.23 mode, the WDSZ bits set the number of data bits per character as follows:...

  • Page 53: Software Interface Considerations

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 3.2 SOFTWARE INTERFACE CONSIDERATIONS 3.2.1 Parallel Data Transfer Register 10 in the interface memory is the Data Buffer (DBUFF). The modem and host synchronize parallel data transfer by observing the state of the Buffer 2 Available bit, B2A (1E:3). RAM Access 2 is not available when the modem is in parallel data mode.

  • Page 54: Figure 3-2. Parallel Data Transfer Routine

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide START PDM (07:5) SETUP (1F:0) SETUP (1F:0)= 0? TO RECEIVE PARALLEL DATA TO TRANSMIT PARALLEL DATA PERFORM DUMMY READ OF 1 RTSP (07:7) DBUFF (10:7-0) B2A (1E:3)= 1? CTSP (0F:1) = 1? READ DBUFF...

  • Page 55: 8-Bit Audio Mode Operation

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 3.2.3 8-Bit Audio Mode Operation The 8-bit Audio Mode operates when CONF = 82h. Tone Detectors All tone detectors are functional in this mode. 8-Bit Audio Mode Transmitter This mode allows the transmission of 8-bit audio messages.

  • Page 56: Dtmf Receiver

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 3.2.5 DTMF Receiver Mode Selection and Description Configuration code 21h enables the DTMF receiver to operate concurrently with the FSK receiver and the three tone detectors. Configuration codes 90h or 98h and 92h or 94h also enable the DTMF receiver to operate concurrently with the three tone detectors in the Voice Codec and Audio Codec modes.

  • Page 57: Fsk 7E Flag Detector

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 3.2.6 FSK 7E Flag Detector The FSK 7E flag detector can be used to detect the presence of the energy produced by the T.30 FSK 7E flag preamble while the modem is configured in any high speed receiver mode except for V.27 ter short train. FSKFLS and FSK7E bits indicate the status of the detection process (see Table 3-1 for bits description).

  • Page 58: Mode Operation

    During reception, start and stop bits are always stripped by the modem. The parity bit is NOT, in general, stripped from the data by the modem, and remains with the data as the most significant bit, for backward compatibility with previous Rockwell products. In parallel mode, the modem senses overrun, underrun, framing, and parity errors.

  • Page 59: Figure 3-5. V.23 Modes Setup Procedure

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide V.23 Mode Setup Set CONF = 24h Full Duplex Desired? Originate Desired? Set V23HDX = 0, Set V23HDX = 0, Set V23HDX = 1, ANS = 1 ANS = 0 ANS = 0 (for Tx = 1200, Rx = 75)

  • Page 60: High Speed Timing

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Caller ID Setup Set CONF = 22h Set V23HDX = 0, ANS = 0 (Rx = 1200 bps) Set SETUP bit Exit Figure 3-6. Caller ID Mode Setup Procedure 3.2.9 High Speed Timing Several status bits in the DSP interface memory are useful to the host for monitoring various receiver conditions. These bits are significant during training and data reception/transmission.

  • Page 61: Figure 3-7. High Speed Mode Status Bit Timing

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Analog SCR1 DATA Signal TRANSMIT: SIDLE SCR1 DATA/CTSP RECEIVE: SIDLE PNDET PNSUC PNSUC SCR1 DATA/CDET 1070F3-7a HS Timing Figure 3-7. High Speed Mode Status Bit Timing 1070 3-27...
  • Page 62 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Analog Data 8 bits SCR1 Signal T12* (min) RTSP SIDLE SCR1 DATA/CTSP SIDLE PNDET PNDET PNSUC SCR1 DATA/CDET 1070F3-7b HS Timing * See Table 3-2, Note ***. Figure 3-7. High Speed Mode Status Bit Timing (Cont’d)

  • Page 63: Power-On/Reset Dsp Test Mode And Crystal Selection

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 3.2.10 Power-On/Reset DSP Test Mode and Crystal Selection After Power-on or Reset, the modem enters into a test mode and calculates checksums on ROM, RAM and multiplier sections. The results of the checksums and ASCII values corresponding to the DSP device part number and code revision letter are written to the interface memory registers 10h through 19h approximately 20 milliseconds after Power-on/Reset signal goes off (see Table 3-3).
  • Page 64 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide This page is intentionally blank. 3-30 1070...

  • Page 65: Dsp Ram Access

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 4. DSP RAM ACCESS The DSP contains 16-bit words of random access memory (RAM). Because the DSP is optimized for performing complex arithmetic, the RAM is organized into real (X RAM) and imaginary (Y RAM) parts. The host processor can read or write both the X RAM and the Y RAM.

  • Page 66: Dsp Ram Write Procedure

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 4.1.4 DSP RAM Write Procedure The RAM write procedure is a 16-bit transfer from interface memory to DSP RAM allowing the transfer of X RAM data or Y RAM data to occur each baud data, or sample time (Figure 4-1).

  • Page 67: Table 4-1. Modem Dsp Ram Access Codes

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 4-1. Modem DSP RAM Access Codes Function SBRAMx AREXx ADDx Read Reg. No. 4 Received Signal Sample (Pre-AGC) Received Signal Sample (Post-AGC) Received Signal Sample - 8-bit Audio Mode (Post-AGC) Average Energy AGC Gain Word...

  • Page 68: Table 4-2. Modem Dsp Ram Access Codes - Sbram

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide . Modem DSP RAM Access Codes (Cont’d) Table 4-1 Function SBRAMx AREXx ADDx Read Reg. No. 4 Voice/Audio VOX Turn-On Threshold Voice/Audio VOX Turn-Off Threshold Voice/Audio VOX A0 Filter Coefficient Voice/Audio VOX A1 Filter Coefficient...

  • Page 69: Figure 4-1. Host Flowchart - Ram Data Read And Ram Data Write

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Start Read Start Write ACCx = 0 ACCx = 0 WRTx = 0 Store relevant access code in ADDx , AREXx, SBADxM and SBADxL Read YDALx to reset BxA CRx, IOx, and SBRAMx = 0 or 1...

  • Page 70: Diagnostic Data Scaling

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 4.2 DIAGNOSTIC DATA SCALING No. 1a Received Signal Sample (Pre-AGC) = A/D Sample Word Format: 16 bits, signed, twos complement Equation: V INT (Volts)= [(A/D Sample Word x V MAX /32768) + 2.5V Where: V MAX = 1.0V @ 9600 Hz sample rate...
  • Page 71 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide No. 6a IIA Tone 1 Frequency No. 6b XIA Tone 1 Frequency No. 8a IIA Tone 2 Frequency No. 8b XIA Tone 2 Frequency Format: 16 bits, unsigned Equation: N = 6.8267 x Frequency (in Hz) for 9600 Hz sampling rate N = 8.192 x Frequency (in Hz) for 8000 Hz sampling rate...
  • Page 72 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide No. 14 Error Vector Represents the difference between the received point (P2) and the nearest ideal point (P1). Format: 16 bits, signed, twos complement, real 16 bits, signed, twos complement, imaginary BOUNDARY ε + iy + iy ε...
  • Page 73 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide No. 15 Rotation Angle Represents instantaneous correction for phase and frequency errors. Format: 16-bits, twos complement Equation: Rotation Angle (degrees) = [(Rotation Angle Word)h/10000h] x 180 No. 16 Frequency Correction Represents component of rotation angle caused by frequency error.
  • Page 74 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide No. 30 Minimum Off-Time (DTMF) The minimum off-time is defined as the minimum period of time of the DTMF signal beginning when the energy falls below the turn-off threshold and ending when a gain hit is detected. The off-time parameter is equal to the desired minimum off- time minus the drop out time.
  • Page 75 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide No. 35 Frequency Deviation, High Group (DTMF) This parameter controls the acceptable frequency range for the high group DTMF tones. Increasing the value of this parameter increases the frequency range. The frequency range will vary from one DTMF symbol to another. To increase or decrease the parameter value, convert the increase/decrease into hex and add/subtract to/from the current value.
  • Page 76 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide No. 40 Transmitter Rate Sequence Pattern (RFX144 models only) No. 41 Receiver Rate Sequence Pattern (RFX144 models only) The following rate sequence patterns can be sent and detected by the modem as enabled by the ASPEED bit (see ASPEED...
  • Page 77 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide No. 50 Sleep Mode Writing a 0 to this register when the modem IA circuit is not in the Sleep Mode (see ~SLEEP pin in Table 2-3) puts the modem into the Sleep Mode.
  • Page 78 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide No. 57 Voice/Audio VOX A0 Filter Coefficient The VOX energy averaging filter coefficient A0 is a function of the filter time constant. Format: 16 bits, signed, twos complement Equation: A0 = 917.5/x Where: x = VOX turn-off time constant in seconds.
  • Page 79 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide No. 62 Voice/Audio Energy AGC Maximum Gain Word Maximum gain for the Energy AGC. The default value is loaded each time the modem is configured to Voice Codec Modes (CONF = 90h or 98h) or Audio Codec Mode (CONF = 92h or 94h).
  • Page 80 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide No. 68 Room Monitor Volume Control The amplitude of the IIA DAC signal in the Room Monitor Mode can be adjusted. An increase in the value written to the modem shifts the value sent to the IIA DAC left by one, thereby doubling its amplitude.
  • Page 81 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide No. 72 Speakerphone Line Echo Suppresser Speakerphone line echo suppresser is a switching loss inserted in the receive (speaker) path and is enabled only in the transmit mode (Transmit_Speech_Active = 1, Receive_Speech_Active = 0.) The loss should be kept just necessary so that the hybrid residual echo will not be heard at maximum speaker volume control setting.
  • Page 82 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide No. 77 Speakerphone Transmit Speech Hangover In order to avoid choppy sounds for weak voice signals whose energy is not much different from the noise floor, a minimum ON time (hangover) is usually added to the speech detector. When speech is gone, the hangover will be gradually decremented to 0.

  • Page 83: Hdlc Framing

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 5. HDLC FRAMING The modem supports HDLC framing. High Level Data Link Control) protocol is a standard procedure used for data communications. SDLC (Synchronous Data Link Control) is a bit-oriented protocol which is a subset of HDLC. The same format is used in both protocols although all SDLC fields must be eight-bit octets.

  • Page 84: Frame Abortion, Frame Idle, And Time Fill

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Information Field The modem treats the address field, the control field, and any other transmitted data, except for the flags and the Frame Check Sequence, as the information field. The information field does not have a set length; however, this field follows the SDLC protocol in being in the format of eight bit bytes.

  • Page 85: Implementation

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 5.2 IMPLEMENTATION A representation of the HDLC process is shown in Figure 5-3. The events are numbered in order of occurrence from one to four. The beginning flag is transmitted. The receiver sees the flag and now becomes aligned with the transmitter. Both the receive and the transmitter FCS registers are preset to FFFFh.

  • Page 86: Figure 5-4. Hdlc Signals Timing

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 1 , 7 RTSP CTSP SCR1 S FLAGS D1 D2 D3 D1 D2 A D1 D2 D3 D1 A D1 D2 SCR1 s ~IRQx ABIDL ZEROC OVRUN FLAG Transmitter Mode Control 1. Upon setting RTSP, the host should initialize EOF, ABIDL, ZEROC, and OVRUN to the desired values.

  • Page 87: Mode Selection

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 5.2.1 Mode Selection In order to use HDLC in the modem, the host processor must: Set up the modem configuration. Set the parallel data mode bit (PDM). Set the HDLC mode bit. Set the SETUP bit.

  • Page 88: Flag Transmission And Reception

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 5.2.4 Flag Transmission and Reception The modem transmitter sends at least one flag as the opening flag of the first frame. As long as the user does not load the 8-bit transmit data register, DBUFF (register 10h), with data, the modem sends continuous flags with no zero-sharing (i.e., 0111111001111...).

  • Page 89: Fcs And Ending Flag Transmission And Reception

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide first byte of data of the next frame into DBUFF. If the host wants to end transmission, the host must wait for EOF to return low before turning off RTS or ~RTS. The automatic frame ending feature can be used to more easily facilitate the use of a DMA interrupt system. With this feature, data is transmitted as described in the above paragraph.

  • Page 90: Underrun And Overrun Conditions

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide The reception of data immediately following the abort/idle sequence is treated as invalid and is not presented to the user. Therefore, to re-establish transmitter and receiver synchronization, the receiver must see at least one flag. At least one flag and three bytes of data must be received following the abort sequence before any data is given to the host.
  • Page 91 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Receiver Example The steps to perform a typical HDLC reception are: Set the modem configuration to the desired speed for receiving, enable HDLC, and parallel data mode. Perform a dummy read of DBUFF to reset B2A.
  • Page 92 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide This page is intentionally blank. 5-10 1070...

  • Page 93: Tone Detector Filter Tuning

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 6. TONE DETECTOR FILTER TUNING This section describes a method of tuning the filters in the modem for tone detection. This method is the same as for other MONOFAX modems. 6.1 PROGRAMMABLE TONE DETECTORS The modem includes three independently programmable tone detectors (F1, F2, and F3).
  • Page 94 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Filter 1 has a transfer function: + α + α (Z) = 2(α )/(1 - 2β - 2β (Eq. 1) Filter 2 has a transfer function: + α’ + α’ (Z) = 2(α’ )/(1 - 2β’...
  • Page 95 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide From Equation 8: β = β’ = -r /2 = -0.494048699 Rewriting Equation 7 in terms of the offsets ƒ A and ƒ’ A: β = r cos [360° (ƒ - ƒ )/ƒ (Eq. 9) β’...

  • Page 96: Figure 6-2. Typical Single Filter Response

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 1000 2000 3000 3500 FREQUENCY (Hz) 1070F6-2 Figure 6-2. Typical Single Filter Response 1000 2000 3000 3500 FREQUENCY (Hz) 1070F6-3 Figure 6-3. Typical Cascade Filter Response 1070...

  • Page 97: Figure 6-4. Z-Plane Pole-Zero Diagram

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Im Z 90° F s /4 Hz UNIT CIRCLE r = 1 + j1 CONJUGATE POLE PAIR TONE DETECTOR CIRCLE r = 0.994030884 r = 0.994030884 β + 2β β θ 360° 180° θ...

  • Page 98: Figure 6-5. Bandwidth And Offset Frequencies

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide COMPACTOR THRESHHOLD OVERALL CASCADE RESPONSE FILTER 1 FILTER 2 ƒ O - B ƒ O + B ƒ O - ƒ A ƒ O ƒ O + ƒ A FREQUENCY (Hz) 1070F6-5 Figure 6-5. Bandwidth and Offset Frequencies EQ.

  • Page 99: Filter Coefficients

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 6.1.3 Filter Coefficients Table 6-1 contains the RAM access codes for all filter coefficients. Refer to the Section 4 for the proper procedure for writing new coefficients into the RAM locations. Table 6-2 contains the computed values of the filter coefficients, including those of default frequencies 462 Hz, 1100 Hz, and 2100 Hz.

  • Page 100: Table 6-2. Calculated Coefficient Values, 9600 Hz Sample Rate

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 6-2. Calculated Coefficient Values, 9600 Hz Sample Rate Frequency Detected Coefficient Name Coefficient Value (Hex) Coefficient Value (Decimal) 2100 Hz ±25 Hz; ƒ A ≅18 Hz α 0 = α' 0 0198 0.01245117 α...

  • Page 101: Table 6-3. Calculated Coefficient Values, 8000 Hz Sample Rate

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 6-3. Calculated Coefficient Values, 8000 Hz Sample Rate Frequency Detected Coefficient Name Coefficient Value (Hex) Coefficient Value (Decimal) 2100 Hz ±25 Hz; ƒ A ≅18 Hz α 0 = α' 0 0198 0.01245117 α...

  • Page 102: Table 6-4. Calculated Coefficient Values, 4000 Hz Sample Rate

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 6-4. Calculated Coefficient Values, 4000 Hz Sample Rate Frequency Detected Coefficient Name Coefficient Value (Hex) Coefficient Value (Decimal) 1650 Hz; ƒ A ≅ 18 Hz α 0 0097 0.00460815 α 1 0000 0.00000000 α...

  • Page 103: Dtmf Dialing With Auto Dialer

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 7. DTMF DIALING WITH AUTO DIALER The modem includes tunable oscillators that can be used to perform dual-tone multi-frequency (DTMF) dialing. The frequency and amplitude of each oscillator output is under host control. A programmable tone detector can also be used in call establishment to recognize an answer tone.

  • Page 104: Detecting Answer Tone

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide The hexadecimal numbers written into these RAM locations are scaled as follows: Frequency number = 6.8267 x 8.192 x (desired frequency in Hz) for 9600 Hz sample rate, or 8.192 x (desired frequency in Hz) for 8000 Hz sample rate.

  • Page 105: Table 7-2. Dtmf Parameters

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 7-2. DTMF Parameters Digit AREXx ADDx Value (Hex) (Hex) 1918 23A0 65AB 7FFF 1296 203D 65AB 7FFF 1296 23A0 65AB 7FFF 1296 2763 65AB 7FFF 1488 203D 65AB 7FFF 1488 23A0 65AB 7FFF...

  • Page 106: Single Tone Generation

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 7-2. DTMF Parameters (Cont’d) Digit AREXx ADDx Value (Hex) (Hex) 1918 203D 65AB 7FFF 1918 2763 65AB 7FFF 1296 2B8C 65AB 7FFF 1488 2B8C 65AB 7FFF 16B8 2B8C 65AB 7FFF 1918 2B8C 65AB 7FFF 7.5 SINGLE TONE GENERATION...

  • Page 107: Figure 7-1. Autodialer Flowchart

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide AUTODIAL Request phone number from input device and load number buffer REDIAL REDIAL Save interrupt status and disable interrupts Save current configuration and select DTMF transmit configuration Set DAA to off-hook Request coupler cut through from DAA...
  • Page 108 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide DIAL Read next BYTE from number buffer 2Fh<BYTE<3Ah? BYTE = 2Ch? Print BYTE Select one set of four coefficents from Delay for 2 seconds Table 7-2 based on value of BYTE Store four coefficents in RAM using RAM write routine of Figure 4-2 1 ->...
  • Page 109 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide ANS.DET Select FSK Configuration Print "WAITING FOR ANSWER" Start 3 second timer FR1 (08:5) = 1? Time out? Print "ON-LINE" Print "NO ANSWER" Restore modem configuration and set DAA to on-hook Restore interrupt status...
  • Page 110 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide This page is intentionally blank. 1070...

  • Page 111: Voice Codec And Audio Codec Modes With Room Monitor

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 8. VOICE CODEC AND AUDIO CODEC MODES WITH ROOM MONITOR The voice codec compresses voice with near toll quality playback at an average rate of 2.9 kbps (CONF=90h) or at a fixed rate of 4.7 kbps (CONF=98h). An average rate of 2.9 kbps provides 24 minutes of stored voice messages in 4 Mbits of memory.

  • Page 112: Figure 8-1. Encoder Implementation

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide START B2A(1E:3)=1? Set/reset RMM(07:5), Codecs (07:6) READ ENCODER OUTPUT, DBUFF(10:0-7) CONF (06:0-7)= 90/92/94/98h TONE TRANSMIT SETUP(1F:0)=1 RTSP(07:06)=1 RTSP(07:6)=0 SETUP=0? VOVUN(17:3)=1? WRITE DTMF DETECT, TONE TRANSMIT, TONE DETECT, AGC, VOX, ETC. PARAMETERS AS NEEDED DTMF DETECT,...

  • Page 113: Voice And Audio Activated Message Encoding

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 8.1.1 Voice and Audio Activated Message Encoding Voice and Audio activated recording maximizes RAM storage efficiency. By setting control bit VOXREC (1A:3) before enabling the encoder, the host automatically eliminates beginning of message silence or background noise by delaying encoding until status bit VOX (17:3) is set.

  • Page 114: Figure 8-2. Agc Operation

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide START AGC RMS ENERGY CALCULATION AGCSEL(14:6)=1? ENUPDT(14:5)=1 ENERGY > AGC ADAPTATION THRESHOLD? VOICE CLASSIFIER ENERGY > AGC ADAPTATION G=G+(E-Eref)SR THRESHOLD (see note) UPDATE AGC GAIN? DCVOX(14:5)=1? ADVANCED GAIN ADAPTATION VOX(17:3)=1? APPLY AGC GAIN TO INPUT...

  • Page 115: Figure 8-3. Agc Implementation

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide REFERENCE MESSAGE AGC ENERGY AGC GAIN ADAPTATION ENCODING REFERENCE LEVEL THRESHOLD MAXIMUM GAIN = DISABLE AGC ENABLE AGC 0000h/7FFFh INCREASE OR ENABLE AGC DECREASE LEVEL AT RIN AS NEEDED ENCODE A MESSAGE WITH UNIFORM...

  • Page 116: Figure 8-4. Agc Implementation

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide AGC MAXIMUM GAIN AGC SLEW RATE SLEW RATE = 7FFFh ENABLE AGC ENABLE AGC ENCODE A MESSAGE WITH UNIFORM ENERGY LEVEL DISTINCTIVELY LESS THAN REFERENCE ENCODE A MESSAGE ENERGY LEVEL WITH UNIFORM ENERGY LEVEL...

  • Page 117: Figure 8-5. Agc Parameters Operating Envelope

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Energy Reference Level Output (dB) Maximum Gain Gain Adaptation Threshold 1070F8-5 Gain Energy Energy Energy Adaptation Reference Reference Reference Threshold Level Level - Level Maximum +25 dB Gain Input (dB) Figure 8-5. AGC Parameters Operating Envelope...
  • Page 118 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Energy Reference Level The Energy Reference Level establishes the desired playback energy level. Input with energy greater than the Energy Reference Level will be attenuated. Input with energy less than the Energy Reference Level will be increased.

  • Page 119: Voice Decoder And Audio Decoder

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 8.2 VOICE DECODER AND AUDIO DECODER Decoder error correction coding must be enabled for voice decoder playback of messages compressed with error correction and disabled for messages compressed without error correction (see control bit HDLC in Table 3-1).

  • Page 120: Figure 8-6. Decoder Implementation

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide START B2A (1E:3)=1? SET/RESET RMM (07:5), CODECS (07:6) DECODER PAUSE OR END PLAYBACK? CONF (06:0-7)= 90/92/94/98h WRITE DECODER INPUT, DBUFF (10:0-7) SETUP (1F:0)=1 VOVUN (17:3)=1? SETUP=0? WRITE DTMF DETECT, TONE DETECT, ETC. CHANGE PLAYBACK...

  • Page 121: Error Correction Coding And Aram Message Storage

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 8.3 ERROR CORRECTION CODING AND ARAM MESSAGE STORAGE The host enables voice encoder error correction coding by setting control bit HDLC (7:0) prior to message encoding. Optional error correction coding allows message storage in audio-grade random access memories (ARAMs) at an average rate of less than 3.15 kbps or at a fixed rate of 5.0 kbps.

  • Page 122: Tone Detection

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide The timer expires. The IIA input is switched to the Line IN, control bit RMM is reset, and voice or audio codec configuration selected. Go to step 2 or go to step 4 with timer reinitialized to same Room Monitor period.

  • Page 123: Implementation

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 9. T.30 IMPLEMENTATION 9.1 GENERAL CCITT Recommendation T.30 details procedures for facsimile transmission over the PSTN. This standard describes how to initiate, complete, and end a fax transmission. This section describes methods to set up host software to implement T.30.

  • Page 124: Figure 9-1. Basic Block Diagram Of G3 Facsimile

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide PHOTOELECTRIC DATA DOCUMENT MODULATOR CONVERSION COMPRESSION TX SCANNING CONTROL RECEIVED PRINTER DATA DEMODULATOR IMAGE CONVERSION DECODING RX SCANNING CONTROL 1070F9-01 Basic Figure 9-1. Basic Block Diagram of G3 Facsimile CALLING UNIT CALLED UNIT CALLING TONE: 1100 Hz, 0.5S ON/3S OFF...

  • Page 125: Figure 9-3. Transmit Calling Tone (Cng) (1100 Hz)

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide PHASE A START DISABLE DIAGNOSTICS 1 CONFIGURE FOR ACC1 TONE TRANSMIT CONF (6:0-7) SETUP (1F:0) LOAD RAM ADDRESS & AREX1; RESET CR1, BR1, & DR1 ADD1 AREX1 SETUP = 0? DISABLE LOAD PARAMETERS DIAGNOSTICS 1...

  • Page 126: Figure 9-4. Detecting Cng Tone (1100 Hz)

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide PHASE A START CONFIGURE FOR FSK CONF (6:0-7) SETUP (1F:0) SETUP = 0? MONITOR FR2 BIT FR2 (8:6) = 1? TIME OUT DELAY 600ms 3 SECONDS? CHECK FR2 BIT FR2 = 0? DELAY 3.6...

  • Page 127: Figure 9-5. Transmit Called Tone (Ced) (2100 Hz)

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide PHASE A START CONFIGURE FOR DISABLE TONE TRANSMIT DIAGNOSTICS 1 CONF (6:0-7) ACC1 SETUP (1F:0) LOAD RAM ADDRESS & AREX1 RESET CR1, BR1 & DR1 ADD1 SETUP = 0? AREX1 DISABLE DIAGNOSTICS 1 LOAD PARAMETERS...

  • Page 128: Figure 9-6. Detecting Ced Tone (2100 Hz)

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide PHASE A START CONFIGURE FOR FSK CONF (6:0-7) SETUP (1F:0) SETUP = 0? MONITOR FR1 BIT FR1 (8:5)=1? DELAY TIME OUT? 2.6 SECONDS CHECK FR1 BIT FR1 = 1? CED NOT DETECTED CED DETECTED 1070F9-6 Figure 9-6.

  • Page 129: Figure 9-7. Hdlc Frame Structure

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide PREAMBLE BINARY CODED INFO NSF FRAME CSI FRAME DIGITAL ID FRAME (OPTIONAL) (OPTIONAL) (MANDATORY) FLAG ADDRESS CONTROL FLAG 01111110 11111111 1100X000 01111110 8 BIT 8 BIT 8 BIT 8 BIT 32 BIT 16 BIT 8 BIT FCS: Frame check sequence;...

  • Page 130: Phase B

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide During TCF, EQMs that represent acceptable BERs can be used to determine whether or not to fallback. If a fallback is necessary, EQM can be used to choose the appropriate fallback mode for a desired BER.
  • Page 131 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide The hardware ~IRQ1 pin must be monitored for interrupts. The ~IRQ1 pin will become active (go low) when the modem is ready for a byte of data. This data should be loaded into the Data Buffer Register, DBUFF. When the ~IRQ1 returns low, the modem is ready for the next byte of data.

  • Page 132: Figure 9-8. Phase C Format

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide RETURN TO CONTROL (RTC) INDICATING END OF DOCUMENT TRANSMISSION FORMAT: SIX CONSECUTIVE EOLS. START OF PHASE C DATA DATA FILL DATA ≥ T ≤ T ≥ T T MINIMUM TRANSMISSION TIME OF A TOTAL CODED SCAN LINE.

  • Page 133: Figure 9-9. Transmit Fsk/Hdlc Signals

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide START LOW SPEED CONFIGURATION TX PREAMBLE ENABLE BUFFER 2 INTERRUPT 1 B2I1E (1E:5) INITIALIZE BYTE COUNT IRQ TX ROUTINE EOF = 0 RESET RTSP RTSP (7:7) 1070F9-9 Figure 9-9. Transmit FSK/HDLC Signals 1070 9-11...

  • Page 134: Figure 9-10. Setup For Programmable Interrupt

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide PROGRAMMABLE INTERRUPT SET-UP ENABLE PROGRAMMABLE INTERRUPT PIE (1F:4) PIDR (5;5) LOAD REGISTER ADDRESS ITADRS (A:0-4) SPECIFY BITS TO BE MASKED ITBMSK (B:0-7) RESET ANDOR BIT ANDOR (A:5) SET FOR DC TRIGGERED TRIG (A:7-6) 1070F9-10 Figure 9-10.

  • Page 135: Figure 9-11. Low Speed Configuration Subroutine

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide LOW SPEED CONFIGURATION CONFIGURE FOR V.21 FSK CONF (06:0-7) SETUP FOR PARALLEL DATA MODE PDM (7:5) ENABLE HDLC MODE HDLC (7:0) AEOF (15:5) SETUP (1F:0) PROGRAMMABLE INTERRUPT SETUP SETUP = 0? 1070F9-11 Figure 9-11. Low Speed Configuration Subroutine.

  • Page 136: Figure 9-12. Transmit Preamble

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide TRANSMIT PREAMBLE SET RTSP RTSP (7:7) LOAD 7Eh INTO DBUFF REGISTER WAIT FOR CTSP CTSP (F:1) =1? DELAY 1 SECOND 1070F9-12 Figure 9-12. Transmit Preamble 9-14 1070...

  • Page 137: Figure 9-13. Low Speed Interrupt-Driven Transmit

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide IRQ TX ROUTINE WAIT FOR INTERRUPT ~IRQ1=0 POLL ERROR INTERRUPT BUFFER 2 AVAILABLE NOT CAUSED BY B2A(1E:3) MODEM LOAD DATA INTO BUFFER 2 DECREMENT BYTE COUNT MORE TO TRANSMIT BYTE COUNT SET END OF...

  • Page 138: Figure 9-14. Receive Fsk/Hdlc Signals

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide START LOW SPEED CONFIGURATION ENABLE BUFFER 2 INTERRUPT 1 B2I1E (1E:5) IRQ LOW SPEED RX ROUTINE CHECK IF FRAME IS IN ERROR CRC (9:1) RESET EOF BIT RESET EOF BIT EOF (9:2) EOF (9:2)

  • Page 139: Figure 9-15. Low Speed Interrupt-Driven Receive

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide IRQ LOW SPEED RX ROUTINE WAIT FOR INTERRUPT ~IRQ1 = 0? POLL BUFFER 2 AVAILABLE BIT B2A (1E:3) = 1? POLL PROGRAMMABLE READ DATA IN INTERRUPT DBUFF REGISTER REQUEST BIT PIREQ (1F:3) = 1?

  • Page 140: Figure 9-16. High Speed Configuration Setup

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide HIGH SPEED CONFIGURATION CONFIGURE FOR HIGH SPEED CONF CODE FROM TABLE 3-1 CONF (6:0-7) 14400 TO 2400 BPS DISABLE HDLC MODE HDLC (7:0) SETUP (1F:0) SETUP = 0? 1070F9-16 Figure 9-16. High Speed Configuration Setup...

  • Page 141: Figure 9-17. Transmitting Tcf

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide START HIGH SPEED CONFIGURATION SETUP RTSP RTSP (7:7) PRELOAD 00 INTO DBUFF WAIT FOR CTSP TO BE SET CTSP (F:1) DELAY 1.5 SECONDS RESET RTSP RTSP 1070F9-17 Figure 9-17. Transmitting TCF 1070 9-19...

  • Page 142: Figure 9-18. High Speed Message Transmission

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide START HIGH SPEED CONFIGURATION SETUP RTSP RTSP (7:7) PRELOAD DBUFF WITH DUMMY DATA WAIT FOR CTSP TO BE SET CTSP (F:1) ENABLE BUFFER 2 INTERRUPT 1 B2I1E(1E:5) INITIALIZE BYTE COUNT HIGH SPEED IRQ TX ROUTINE...

  • Page 143: Figure 9-19. High Speed Interrupt-Driven Transmit

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide HIGH SPEED IRQ TX ROUTINE WAIT FOR INTERRUPT ~IRQ1=0? ERROR: INTERRUPT B2A (1E:3) =1? NOT CAUSED BY MODEM LOAD COMPRESSED T.4 DATA INTO DBUFF DECREMENT BYTE COUNT MORE TO TRANSMIT BYTE COUNT 1070F9-19 Figure 9-19. High Speed Interrupt-Driven Transmit...

  • Page 144: Figure 9-20. High Speed Reception Setup

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide START HIGH SPEED CONFIGURATION ENSURE VALID TRAIN PERFORM DUMMY READ OF DBUFF ENABLE BUFFER 2 INTERRUPT 1 B2I1E (1E:5) IRQ HIGH SPEED RX ROUTINE 1070F9-20 Figure 9-20. High Speed Reception Setup 9-22 1070...

  • Page 145: Figure 9-21. High Speed Interrupt Driven Receive

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide HIGH SPEED IRQ RX ROUTINE WAIT FOR INTERRUPT ~IRQ1=0? B2A (1E:3) =1? READ DATA IN DBUFF REGISTER MORE TO RECEIVE 1070F9-21 Figure 9-21. High Speed Interrupt Driven Receive 1070 9-23...

  • Page 146: Figure 9-22. Valid Training Sequence Check

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide ENSURE VALID TRAIN WAIT FOR SILENCE/IDLE BIT TO BE SET SIDLE(C:0) WAIT FOR TIMEOUT? PNSUC (08:3) VALID INVALID TRAIN TRAIN 1070F9-22 Figure 9-22. Valid Training Sequence Check 9-24 1070...

  • Page 147: Error Correction Mode

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 9.2 ERROR CORRECTION MODE 9.2.1 General The revised T.30 contains an Error Correction Mode (ECM) option. The ECM allows the phase C portion of the facsimile transmission to be encoded in a HDLC framing format using a specified number of bits in the information field. The transmitted high speed message is broken up into a number of frames identified by frame numbers.

  • Page 148: Figure 9-23. Ecm Frame Structure

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide ADDRESS FRAME EOL, TAG, FIELD NUMBER ALIGN BITS FLAG CONTROL FACSIMILE FLAG FIELD DATA CHECK TRAINING 200 MS 7E 256* OCTETS OF DATA PAD BITS 1 FRAME OF DATA FACSIMILE CODED DATA BLOCK (FCD)

  • Page 149: Figure 9-24. Ecm Message Protocol Example

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide MESSAGE, PAGE 0, BLOCK 0 PPS-NULL (TO INDICATE MORE BLOCKS FOR THIS PAGE WILL BE TRANSMITTED) PPR (TO IDENTIFY FRAMES RECEIVED WITH ERRORS) RETRANSMIT MESSAGE FRAMES IN ERROR, PAGE 0, BLOCK 0 PPS-NULL MCF (TO INDICATE NO ERRORS, AND READY TO RECEIVE)

  • Page 150: Figure 9-25. Pps And Ppr Frame Structure

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide FCF1 FCF2 PAGE BLOCK TOTAL # COUNT COUNT OF FRAMES (0-255) (0-255) IN BLOCK (1-256) FSK 300 BPS = FLAG = ADDRESS FIELD = CONTROL FIELD FCS = FRAME CHECK SEQUENCE PPR FRAME STRUCTURE...

  • Page 151: Signal Recognition Algorithm

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 9.3 SIGNAL RECOGNITION ALGORITHM 9.3.1 FSK vs. High Speed A method of determining whether a high speed message or FSK handshaking is being received by the modem is necessary when implementing the T.30 recommendation. When the calling unit transmitter and called unit receiver configure for V.17, V.29, or V.27 ter, sometimes the high speed message may not be received (typically due to a noisy line).

  • Page 152: Figure 9-26. Signal Recognition Algorithm In High Speed Mode

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide START INITIALIZE AND START TIMER1 FSK7E (08:2)=1? PNSUC (08:3)=1? TIMER1 >6.7 SEC “FSK DETECTED” “HIGH SPEED “T.30 TIMEOUT RECONFIGURE TO FSK DETECTOR” ERROR” 1070F9-26 Figure 9-26. Signal Recognition Algorithm in High Speed Mode 9-30...

  • Page 153: Figure 9-27. Fsk Signal Detection Algorithm In Voice Mode

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide START LOAD IN FR1 COEFFICIANTS FOR THE FSK(7E) DETECTION INITIALIZE A TIMER T1 FOR FLAGS DETECTION TIME-OUT T1 EXPIRED? FR1 (O8:5)=1? INITIALIZE A TIMER T2 FOR DEBOUNCING FLAGS FR1 (O8:5)=1? T2 EXPIRED? VOICE MODE...

  • Page 154: Figure 9-28. Cng Detection (1100 Hz) In Voice Mode

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide START SUGGESTED VALUE FOR DIFFERENT TIMERS: CNG ON TIME MIN = 300ms. LOAD IN FR2 COEFFICIENTS FOR CNG ON TIME MAX = 700 ms. CNG TONE DETECTION CNG OFF TIME MIN = 2.5 sec.

  • Page 155: Short Train Example

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 9.4 SHORT TRAIN EXAMPLE An example of the host implementation of V.17 short train in T.30 is shown in Figure 9-29. The diagram shows the proper setting of control bits EQSV, EQFZ (optional), SHTR, and SETUP. The example starts at the beginning of TCF and the time line proceeds down the page from that point.
  • Page 156 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide This page intentionally left blank. 9-34 1070...

  • Page 157: Caller Id

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 10. CALLER ID 10.1 INTRODUCTION Calling Number Delivery (CND), better known as Caller ID, is a telephone service intended for residential and small business customers. It allows the called Customer Premises Equipment (CPE) to receive a calling party's directory number and the date and time of the call during the first silent interval in the ringing cycle.

  • Page 158: Figure 10-1. Daa Circuit Supporting Cnd

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide The calling party's directory number is represented by the remaining words in the data word field. If the calling party's directory number is not available to the terminating central office, the data word field contains an ASCII “O”. If the calling party invokes the privacy capability, the data word field contains an ASCII “P”.

  • Page 159: Daa Requirements

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 10.5 DAA REQUIREMENTS To receive CND information, the modem monitors the phone line between the first and second ring bursts without causing the DAA to go off hook in the conventional sense, which would inhibit the transmission of CND information by the local central office.

  • Page 160: Figure 10-2. Caller Id Example Flowchart

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Check_Ring Printer Fault? Valid ring detected? Start Caller_Id detection (START_CALLER_ID) Decrement the ring counter Ring count finished ? Start to receive the fax message (RX_FAX) Figure 10-2. Caller ID Example Flowchart 10-4 1070...
  • Page 161 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide START_CALLER_ID Check if Time-out? Call_Id Configure for Caller_Id detection Check if RSLD is 22h -> CONF (06:0-7) Read Data Buffer (DBUFF, 10:0-7) Parallel data mode 1 -> PDM (07:5) Is it "Channel seizure" (55h) ? Setup new configuration 1 ->...
  • Page 162 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Check_Caller_Id End Call_Id Disable the CNDEN relay Read data buffer (DBUFF, 10:0-7) Store data into memory Calculate checksum End of Caller_Id message? Indicate caller_Id is done Checksum is correct? Indicate Caller_Id has an error Call_Id Figure 10-2.

  • Page 163: Digital Equalization/High Pass Filter

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 11. DIGITAL EQUALIZATION/HIGH PASS FILTER 11.1 PROGRAMMABLE DIGITAL EQUALIZER (PDE) A programmable digital equalizer is provided in the high speed receiver and transmitter paths as shown in Figure 11-1 and Figure 11-2. The programmable digital equalizer consists of four cascaded biquads. This is similar to the tone detectors when cascaded by enabling bit 12TH.

  • Page 164: Figure 11-1. High Speed And V.21 Receive Signal Path

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide INTEGRATED ANALOG RECEIVER ANALOG LOW PASS CONVERTER FILTER INPUT DIGITAL SIGNAL PROCESSOR OPTIONAL LOW PASS OPTIONAL HIGH PROGRAM. DIG. FILTER PASS FILTER EQUALIZER AUTOMATIC OPTIONAL DIG. TONE GAIN CABLE DETECTOR EQUALIZER CONTROL RECEIVER DIGITAL DATA V.33/V.17, V.29...

  • Page 165: Figure 11-2. High Speed And V.21 Transmit Signal Path

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide INTEGRATED ANALOG RECEIVER LOW PASS ANALOG CONVERTER FILTER INPUT DIGITAL SIGNAL PROCESSOR OPTIONAL DIG. LOW PASS OPTIONAL HIGH CABLE FILTER PASS FILTER EQUALIZER* TRANSMITTER DATA V.33/V.17, V.29 AUTOMATIC DIGITAl OUTPUT V.27 TER, V.21 GAIN...

  • Page 166: Figure 11-4. Pde Response

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide (Default) (Thousands) FREQUENCY (Hz) (Default) -0.1 -0.2 -0.3 (Thousands) FREQUENCY (Hz) 1070F11-4 Figure 11-4. PDE Response 11-4 1070...

  • Page 167: Figure 11-5. Digital Cable Equalizer Frequency Response

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 11-1. PDE Poles and Zeros Section Number Poles Zeros 0.794 @ 1215 Hz 1.26 @ 1215 Hz 0.798 @ 1728 Hz 1.25 @ 1728 Hz 0.793 @ 2241 Hz 1.26 @ 2241 Hz 0.830 @ 2713 Hz...

  • Page 168: Figure 11-6. Receive Path Frequency Response Without Hpf

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide LOG MAGNITUDE (dB) VS FREQUENCY -20dB -40dB -60dB -80dB -100dB FREQUENCY (HERTZ) Figure 11-6. Receive Path Frequency Response without HPF 11-6 1070...

  • Page 169: Figure 11-7. Receive Path Frequency Response With Hpf

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide LOG MAGNITUDE (dB) VS FREQUENCY -20dB -40dB -60dB -80dB -100dB FREQUENCY (HERTZ) Figure 11-7. Receive Path Frequency Response with HPF 1070 11-7...
  • Page 170 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide This page is intentionally blank. 11-8 1070...

  • Page 171: Full-Duplex Speakerphone

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 12. FULL-DUPLEX SPEAKERPHONE 12.1 INTRODUCTION A full-duplex (FDX) speakerphone is a hands-free telephone which allows incoming and outgoing voice to flow spontaneously without noticeable clipping and choppy sound effects. A separate microphone and separate loudspeaker are used instead of a handset.

  • Page 172: Microphone And Speaker Gains

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 12.2.2 Microphone and Speaker Gains When the placements of the microphone and speaker are fixed, the coupling characteristics through open air is basically determined. The analog pre-amplification gain for the selected microphone element must be determined so that the input signal falls within the normal input range of the codec when talking loud at one foot distance from the microphone.

  • Page 173: Fdx Speakerphone Mode

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Bit 5: TONEXE (XIA Tone Enable). When set, tone is generated through the XIA codec DAC. Bit 6: TONEIE (IIA Tone Enable). When set, tone is generated through the IIA codec DAC. Bit 7: N/A (Reserved).

  • Page 174: Microphone Volume Control

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide The acoustic echo canceller is bypassed in the handset mode. However, the coefficients of the canceller are maintained in order for the canceller to resume functioning quickly when configured back to the FDX Speakerphone Mode.

  • Page 175: Microphone And Speaker Muting

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide The default speaker volume control is -10 dB. It is advised to check the dial-tone loudness at this setting. Adjust the volume control, if necessary, to make sure its loudness is at the right level. Disabling the speaker AGC function may be considered during the dial-tone reception.

  • Page 176: Scaling Of Transmit Output To Line

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide minimum on-time is inserted in the speech detector to smooth the switching effect over weak sounds, especially for consonants at the end of a word or sound level very close to the noise floor. Note that the switching here is totally different from that in half-duplex speakerphones where the voice channel is gated.

  • Page 177: Table 12-1. Register Location 0E Use

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 12-1. Register Location 0E Use TTONEE VOLUP VOLDWN SP/HS MUTEI MUTEX MICLVL Mode FDX Speakerphone Tone Transmit Handset Microphone Mute Speaker Mute Notes: “x” means that the corresponding bit is active. Table 12-2. Register Location 0F Use...
  • Page 178 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide This page is intentionally blank. 12-8 1070...

  • Page 179: Performance

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 13. PERFORMANCE 13.1 TYPICAL BIT ERROR RATES Typical bit error rate (BER) performance of the modem is shown in Figure 13-1. Performance is specified for a test configuration conforming to that specified in CCITT Recommendation V.56. Bit error rates are measured for a flat line at a received line signal level of -20 dBm.

  • Page 180: Table 13-1. Dtmf Receiver Performance Characteristics

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 13-1. DTMF Receiver Performance Characteristics Minimum 10 Maximum 10 Characteristic Units Programmable? Notes Acceptable Twist 1, 2, 4, 5, 6, 7, 9 -8.2 ±0.2 +4.3 ±0.2 Acceptable Positive 1, 3, 4, 5, 6, 7, 9 +1.5 to +3.2...

  • Page 181: Figure 13-1. Typical Bit Error Rate (Ber) Curves

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 1e - 1 FLAT LINE, RX LEVEL = -20 dBm EQM v.s. BER 35.00 1e - 2 27.90 24.20 68.70 12.35 22.45 19.40 1e - 3 9.80 19.90 54.80 15.40 7.75 1e - 4 14.00...
  • Page 182 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 1e - 1 FLAT LINE, RX LEVEL = -20 dBm 94.40 16.50 EQM v.s. BER 1e - 2 20.50 74.00 1e - 3 7.90 15.80 30.50 57.70 1e - 4 6.00 12.40 4.80 23.70 45.80...
  • Page 183 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 1e - 1 34.70 FLAT LINE, RX LEVEL = -20 dBm EQM v.s. BER 93.50 1e - 2 10.20 20.80 73.30 1e - 3 16.00 7.90 30.30 57.30 6.00 1e - 4 12.50 45.60 4.75...
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  • Page 185: Modem Interface Circuit

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 14. MODEM INTERFACE CIRCUIT 14.1 CIRCUIT AND COMPONENTS The modem is supplied in a 100-pin PQFP (MDP) and a 28-pin PLCC (XIA) for design into OEM circuit boards. The recommended modem interface circuits shown in Figure 14-1 illustrate the connections and components required to connect the modem to the OEM electronics.

  • Page 186: Figure 14-1. Recommended Modem/Speakerphone Interface Circuit

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Figure 14-1. Recommended Modem/Speakerphone Interface Circuit 14-2 1070...

  • Page 187: Figure 14-2. Typical Line Interface Circuit

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Figure 14-2. Typical Line Interface Circuit Figure 14-3. Typical Interface to External Hybrid 1070 14-3...

  • Page 188: Figure 14-4. Typical Microphone Circuit

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Figure 14-4. Typical Microphone Circuit Figure 14-5. Typical Speaker Circuit 14-4 1070...

  • Page 189: Table 14-1. Typical Modem Interface Parts List

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 14-1. Typical Modem Interface Parts List Component Designation Component Type Description/Part Number Notes Basic Interface See Figure 14-1. C1, C2, C4, C5, C7, C12, C14, C16 Capacitor 0.1 µF ±10%, 50V C6, C11. C15, C17 Capacitor 10 µF ±20%, 25V...
  • Page 190 RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 14-1. Typical Modem Interface Parts List (Cont’d) Component Designation Component Type Description/Part Number Notes Typical Speaker Circuit See Figure 14-5. NPN Transistor MPSA20 PNP Transistor 2N3906 10K Ω ±1%, 1/8W R1, R5, R6, R7, R8, R9 Resistor 1K Ω...

  • Page 191: Table 14-2. Crystal Specifications - 49.92 Mhz/53.76 Mhz - Third Overtone - Surface Mount

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 14-2. Crystal Specifications - 49.92 MHz/53.76 MHz - Third Overtone - Surface Mount Characteristic Value Value Rockwell Part No. 333R45-003 333R45-009 Electrical Frequency 49.92000 MHz nominal 53.76000 MHz nominal Frequency Tolerance ±45 ppm (C = 18 pF) ±45 ppm (C...

  • Page 192: Pc Board Layout Considerations

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 14.2 PC BOARD LAYOUT CONSIDERATIONS Good engineering practices must be adhered to when designing a printed circuit board (PCB) containing a MONOFAX modem. Suppression of noise is essential to the proper operation and performance of the modem itself and for surrounding equipment.

  • Page 193: Electromagnetic Interference (Emi) Considerations

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 14.2.2 Electromagnetic Interference (EMI) Considerations The following guidelines are offered to specifically help minimize EMI generation. Some of these guidelines are redundant or similar to the general guidelines but are mentioned to reinforce their importance.

  • Page 194: Table 14-3. Modem Pin Noise Characteristics

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide Table 14-3. Modem Pin Noise Characteristics Device Function Noise Source Neutral Noise Sensitive Control 36, 47, 72, 94 100-Pin PQFP Eye Pattern 84-85, 89 Line Interface 26, 46 28-29, 38-40 Speaker (Monitor) Interface Serial DTE Interface...

  • Page 195: Package Dimensions

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide 15. PACKAGE DIMENSIONS Package dimensions are shown in Figure 15-1 (100-pin PQFP) and Figure 15-2 (28-Pin PLCC). See detail A CHAM (4X) PIN 1 TOP VIEW SIDE VIEW Millimeters Inches* Dim. Min. Max. Min.

  • Page 196: Figure 15-2. 28-Pin Plcc Dimensions

    RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide SEATING INDEX PLANE CORNER Inches Millimeters α Dim. Min. Max. Min. Max. PIN 1 4.19 0.165 0.180 4.72 D D1 D2 0.020 REF 0.508 REF 0.432 0.017 0.021 0.533 0.495 12.32 12.57 0.485 0.452 REF 11.48 REF...
  • Page 198 Fax: (33) 93 00 33 03 Suite 103 S.A.R.L. Japan Richardson, TX 75080 Tour GAN, 16 Place de IÕIris Rockwell Int'l Japan Co., Ltd. Taiwan Tel : (214) 479-9310 Cedex 13 Shimomoto Building Rockwell Int'l Taiwan Co., Ltd. For more Information:...

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