IDTECH SecureHead SPI User Manual page 10

3. SPI Operation
This section describes SPI (Serial Peripheral Interface), the SPI bus interface timing, communication
protocol, timeouts, and data output format. The following table shows the signals used in the SPI
interface. Note that the connector is an eight-pin Molex 51021-0800.
PIN # Signal
1 SPCK
2 MISO
3 MOSI
4 DAV
5 NCS
6 VIN
7 GND
8 Head Case GND
3.1. SPI Data Transmission
A serial peripheral interface (SPI) is an interface that enables the serial exchange of data between two
devices, one called a master and the other called a slave. The host (master) generates the clock signal
(SPCK) to trigger data exchange on the SPI bus.
During each SPI clock cycle, data are transmitted in both directions at the same time (full duplex
transmission):
• On the MOSI line, the master sends a bit and the slave reads it
• On the MISO line, the slave sends a bit and the master reads it
The SPI bus transmits data in 8-bit data groups, sending data one bit at a time, from MSB to LSB. An
example of bit transmission for byte A and byte B (of two-byte quantity AB) would be
A(bit 7) A(bit 6) ... A(bit 0) B(bit 7) B(bit 6) ... B(bit 0).
3.2. Clock Polarity and Phase
The clock polarity and phase have four different options with respect to the data. The serial clock
input frequency can go up to 1M bps.
• When clock polarity = 0, the base value of the clock is 0
o For clock phase = 0, data are read on the clock's rising edge (low->high
transition) and data are changed on a falling edge (high->low transition).
o For clock phase = 1, data are read on the clock's falling edge and data are
changed on a rising edge.
o When clock polarity = 1, the base value of the clock is 1
o For clock phase = 0, data are read on clock's falling edge and data are
ID TECH SecureHead SPI with TMIV User Manual
Description
Serial Clock Input
Master Input, Slave Output
Master Output, Slave Input
Data Available (output)
Chip Select, Active Low
Voltage Input
Logic Ground
Chassis Ground
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