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Circuit Diagrams and PWB Layouts
SSB: Channel Decoder
1
2
CHANNEL DECODER
B02A
A
B
C
IT11
9T20
RES
3T19
TUN-AGC
100K RES
4
FT42
3T13
IT15
TUN-AGC-MON
BC847BPN
D
7T18-2
5
100K
3
IT26
E
AGC-COMP
RESET-SYSTEM
TDA-IF-AGC
F
4-MHz
SDA-SSB
G
SCL-SSB
IF-P
IF-N
H
I
3139 123 6214.4
1
2
Q529.1E LA
3
4
5
6
+3V3DVB
IT22
6
3T16
IT27
2
7T18-1
BC847BPN
1K0
1
2T24
FT41
100n
IT32
3T26
100R
3T28
100R
2T28
3T61
390R
3T02
2T29
10n
390R
10n
3
4
5
6
7.
99
7
8
9
+1V2-PNX8541
IT41
5T09
FT15
+1V2DVB
120R
FT59
RESERVED
7T25
LD3985M122
1
5
IN
OUT
IT24
IT25
3T20
3
4
INH
BP
100K
COM
IT03
5T08
FT11
+3V3
+3V3DVB
120R
RES
+5V-TUN
+5V-TUN
IT07
3T10
IT10
18K
3T11
IT29
10K
7T17-1
TDA10048HN
IT18
7
FT40
8
41
33
35
34
IT31
39
38
FT17
40
JTAG-TDO-TDA10048
37
10K
36
+3V3DVB
3T18
2
RES
3
FT36
JTAG-TCK-TDA10048
FT37
JTAG-TDI-TDA10048
FT38
JTAG-TMS-TDA10048
FT39
JTAG-TRST-TDA10048
7
8
9
10
11
12
42
AGC_IF
43
AGC_TUN
18
XIN
DEN
MAIN
32
XOUT
20
CLR
0
21
1
22
SADDR
2
23
3
DO
24
SCL
4
I2C ADDRESS 10
25
SDA
5
26
6
27
TCK
7
TDI
GPIO<0:3>
TDO
19
TMS
OCLK
TRST
17
PSYNC
M
VI
16
P
SCL
TUN
15
SDA
IT33
10
11
12
13
2T01 A8
2T04 C8
B02A
2T05 C8
2T07 D8
2T08 D9
2T09 D9
A
2T12 D11
2T13 D11
2T14 D11
2T15 D12
2T16 D11
2T18 E7
2T20 F6
2T21 F6
2T24 F5
2T25 B7
2T26 D3
2T27 B8
B
2T28 H4
2T29 H5
2T31 E2
2T32 A8
2T35 D8
2T36 D9
3T02 H4
3T07 H8
3T08 E7
3T09 E7
3T10 E7
C
3T11 E7
3T13 D2
3T14 D4
3T16 D3
3T18 G8
3T19 D2
3T20 B7
3T21 E3
3T23 F13
3T26 G5
3T28 G5
3T29 H8
D
3T30 H7
3T31 I8
3T32 I13
3T33 I12
3T61 H4
5T08 C8
5T09 A8
7T17-1 F9
7T18-1 D4
7T18-2 D3
7T25 B8
9T20 C2
E
FT11 C8
FT15 A8
FT17 G8
FT36 H8
FT37 H8
FT38 H8
FT39 H8
FT40 F9
FT41 F3
FT42 D2
FT59 A8
RES
FE-ERR
10K
F
IT03 C7
IT07 E9
3T23
IT10 E7
FE-VALID
IT11 C3
IT15 D2
AGC-COMP
IT18 F7
FE-DATA0
IT22 D4
FE-DATA1
IT24 B7
FE-DATA2
IT25 B8
FE-DATA3
IT26 D3
FE-DATA4
IT27 D3
FE-DATA5
FE-DATA6
IT29 E7
G
FE-DATA7
IT31 G6
IT32 G6
IT33 H9
FE-CLK
IT41 A7
FE-SOP
H
+3V3DVB
SCL-TUNER
I
SDA-TUNER
I_17660_004.eps
110308
13
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