Cirrus Logic CS4525 Manual
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Cirrus Logic CS4525 Manual

30 w digital audio amplifier with integrated adc
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30 W Digital Audio Amplifier with Integrated ADC
Digital Amplifier Features
Fully Integrated Power MOSFETs
No Heatsink Required
–
Programmable Power Foldback on
Thermal Warning
–
High Efficiency
> 100 dB Dynamic Range
< 0.1% THD+N @ 1 W
Configurable Outputs (10% THD+N)
1 x 30 W into 4 Ω, Parallel Full-Bridge
–
2 x 15 W into 8 Ω, Full-Bridge
–
2 x 7 W into 4 Ω, Half-Bridge + 1 x 15 W
–
into 8 Ω, Full-Bridge
Built-In Protection with Error Reporting
–
Overcurrent/Undervoltage/Thermal
Overload Shutdown
–
Thermal Warning Reporting
®
PWM Popguard
Click-Free Start-Up
Programmable Channel Delay for System
Noise & Radiated Emissions Management
System Clock
Crystal Driver
Crystal Oscillator Driver
I/O
Stereo
Analog In
Serial Audio
Clocks & Data
Serial Audio
Data I/O
Serial Audio
Clocks & Data
HP Detect/Mute
Reset
Interrupt
I²C or Hardware
Configuration
Preliminary Product Information
http://www.cirrus.com
for Half-Bridge Mode
Multi-bit ΔΣ ADC
Serial Audio Input Port
Serial Audio
Delay Interface
Auxiliary Serial Port
Register /Hardware
Configuration
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2007
ADC Features
Stereo, 24-bit, 48 kHz Conversion
Multi-bit Architecture
95 dB Dynamic Range (A-wtd)
-86 dB THD+N
Supports 2 Vrms Input with Passive
Components
System Features
Asynchronous 2-Channel Digital Serial Port
32 kHz to 96 kHz Input Sample Rates
Operation with On-Chip Oscillator Driver or
Applied SYS_CLK at 18.432, 24.576 or
27.000 MHz
Integrated Sample Rate Converter (SRC)
–
Eliminates Clock-Jitter Effects
–
Input Sample Rate Independent Operation
–
Simplifies System Integration
Spread Spectrum PWM Modulation
–
Reduces EMI Radiated Energy
Low Quiescent Current
(Features continued on
2.5 V to 5 V
Audio
Processing
Parametric EQ
High-Pass
Bass/Treble
Adaptive
Loudness
Compensation
2-Ch Mixer
2.1 Bass Mgr
Sample Rate
Linkwitz-Riley
Crossover
De-Emphasis
Volume
Error Protection
Over Current
Thermal Warning
Under Voltage
Thermal Feedback
(All Rights Reserved)
CS4525
page
8 V to 18 V
Gate
PWM
Drive
Gate
Multi-bit ΔΣ
Drive
Modulator
with
Gate
Drive
Integrated
Converter
Gate
Drive
2)
VP
Amplifier
Out 1
Amplifier
Out 2
Amplifier
Out 3
Amplifier
Out 4
PGND
PWM Modulator
Output 1
PWM Modulator
Output 2
NOVEMBER '07
DS726PP2

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  • Page 1 Thermal Feedback Output 2 Configuration This document contains information for a new product. Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2007 NOVEMBER '07 (All Rights Reserved) http://www.cirrus.com DS726PP2...
  • Page 2 Filters General Description – De-emphasis Filter Selectable Serial Audio Interface Formats The CS4525 is a stereo analog or digital input PWM – Left-Justified up to 24-bit high efficiency Class D amplifier audio system with an – I²S up to 24-bit integrated stereo analog-to-digital (A/D) converter.

  • Page 3: Table Of Contents

    CS4525 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE MODE ..................8 2. PIN DESCRIPTIONS - HARDWARE MODE ..................10 2.1 Digital I/O Pin Characteristics ......................12 3. TYPICAL CONNECTION DIAGRAMS ....................13 4. TYPICAL SYSTEM CONFIGURATION DIAGRAMS ................15 5.
  • Page 4 CS4525 6.2.2.2 Recommended Power-Down Sequence ..............55 6.2.3 Input Source Selection ......................55 6.2.4 PWM Channel Delay ......................55 6.2.5 Digital Signal Flow ........................ 56 6.2.5.1 High-Pass Filter ......................56 6.2.5.2 Mute Control ......................56 6.2.5.3 Warning and Error Reporting ..................56 6.2.6 Thermal Foldback .........................
  • Page 5 CS4525 9.5.6 Ramp Speed (RmpSpd[1:0]) ....................75 9.6 Mixer / Pre-Scale Configuration (Address 06h) ................75 9.6.1 Pre-Scale Attenuation (PreScale[2:0]) .................. 75 9.6.2 Right Channel Mixer (RChMix[1:0]) ..................76 9.6.3 Left Channel Mixer (LChMix[1:0]) ..................76 9.7 Tone Configuration (Address 07h) ....................76 9.7.1 De-Emphasis Control (DeEmph) ..................
  • Page 6 CS4525 9.19.1 Automatic Power Stage Retry (AutoRetry) ................. 88 9.19.2 Enable Over-Current Protection (EnOCProt) ..............88 9.19.3 Select VD Level (SelectVD) ....................88 9.19.4 Power Down ADC (PDnADC) ..................... 88 9.19.5 Power Down PWM Power Output X (PDnOutX) ..............88 9.19.6 Power Down (PDnAll) ......................
  • Page 7 CS4525 Figure 17.Peak Signal Detection & Limiting ....................37 Figure 18.Foldback Process ........................40 Figure 19.Popguard Connection Diagram ....................46 Figure 20.2-Channel Full-Bridge PWM Output Delay ................50 Figure 21.3-Channel PWM Output Delay ....................50 Figure 22.Typical SYS_CLK Input Clocking Configuration ............... 54 Figure 23.Hardware Mode PWM Output Delay ..................

  • Page 8: Pin Descriptions - Software Mode

    CS4525 1. PIN DESCRIPTIONS - SOFTWARE MODE OUT1 PGND PGND LRCK OUT2 SCLK SDIN Thermal Pad HP_DETECT/MUTE OUT3 PGND PGND DGND OUT4 VD_REG Top-Down (Through Package) View 48-Pin QFN Package Pin Name Pin # Pin Description Interrupt (Output) - Indicates an interrupt condition has occurred.
  • Page 9 CS4525 VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying 5.0 V to VD, LVD must be connected to VD. When applying 2.5 V or 3.3 V to VD, LVD must be DGND. DGND Digital Ground (Input) - Ground for the internal logic and digital I/O.

  • Page 10: Pin Descriptions - Hardware Mode

    CS4525 2. PIN DESCRIPTIONS - HARDWARE MODE CLK_FREQ0 OUT1 CLK_FREQ1 PGND ADC/SP PGND LRCK OUT2 SCLK SDIN Thermal Pad MUTE OUT3 PGND PGND DGND OUT4 VD_REG Top-Down (Through Package) View 48-Pin QFN Package Pin Name Pin # Pin Description CLK_FREQ0...
  • Page 11 CS4525 VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying 5.0 V to VD, LVD must be connected to VD. When applying 2.5 V or 3.3 V to VD, LVD must be con- nected to DGND.

  • Page 12: Digital I/O Pin Characteristics

    CS4525 Digital I/O Pin Characteristics The logic level for each input is set by its corresponding power supply and should not exceed the maximum ratings. Power Pin Name Driver Receiver Supply Number Software Mode Output 2.5 V-5.0 V, Open Drain Input 2.5 V-5.0 V, with Hysteresis...

  • Page 13: Typical Connection Diagrams

    CS4525 3. TYPICAL CONNECTION DIAGRAMS +8 V to +18 V +3.3 or +5 V 10 µF 0.1 µF 470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 470 µF Analog Audio Inputs RAMP_CAP Analog AINL Audio Switch AINR OUT1...

  • Page 14: Figure 2.Typical Connection Diagram - Hardware Mode

    CS4525 +8 V to +18 V +3.3 or +5 V 10 µF 0.1 µF 470 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 470 µF Analog RAMP_CAP Audio Inputs Analog AINL Audio OUT1 Output Switch AINR Filter OUT2 Analog...

  • Page 15: Typical System Configuration Diagrams

    CS4525 4. TYPICAL SYSTEM CONFIGURATION DIAGRAMS 2 x 7 W Stereo + 1 x 15 W Subwoofer Main Tuner Monitor Out CS4525 PIP Tuner Analog In Left Gate Drive Digital In Speaker A/V In 1 Digital Out Control Control Port...

  • Page 16: Figure 5.Typical System Configuration 3

    CS4525 2 x 30 W Stereo + 1 x 30 W Subwoofer Main Tuner Monitor Out Analog PIP Tuner Var/Fixed Out Sound CS4525 Processor A/V In 1 Analog In Analog Gate Drive A/V Switch Digital In A/V In 2 Control...

  • Page 17: Figure 6.Typical System Configuration 4

    CS4525 2 x 15 W Bi-Amp Stereo with Subwoofer Output Main Tuner Monitor Out Analog PIP Tuner Var/Fixed Out Sound CS4525 Processor A/V In 1 Analog In Analog Gate Digital Drive Digital In A/V Switch Left A/V In 2 Control...

  • Page 18: Characteristics And Specifications

    CS4525 5. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS AGND = DGND = PGND = 0 V; all voltages with respect to ground. Parameters Symbol Units DC Power Supply Digital and Analog Core (Note 1) 2.375 2.625 3.135 3.465 4.75 5.25 Amplifier Outputs 18.0...
  • Page 19 CS4525 ANALOG INPUT CHARACTERISTICS Test Conditions (unless otherwise specified): AGND = DGND = PGND = 0 V; All voltages with respect to ground; = 25°C; VD = 3.3 V; Input Signal: 1 kHz sine wave through the recommended passive input filter shown in...
  • Page 20 CS4525 PWM POWER OUTPUT CHARACTERISTICS Test Conditions (unless otherwise specified): AGND = DGND = PGND = 0 V; All voltages with respect to ground; = 8 Ω for full-bridge, R = 4 Ω for half-bridge and parallel full-bridge; = 25°C; VD = 3.3 V; VP = 18 V; R OutputDly[3:0] = 1111;...

  • Page 21: Figure 7.Serial Audio Input Port Timing

    XTI/XTO pins or the input SYS_CLK signal. is the number of bits per sample of the serial digital input. bits 10. After powering up the CS4525, RST should be held low until the power supplies and clocks are stable. LRCK s(LK-SK)

  • Page 22: Figure 8.Aux Serial Port Interface Master Mode Timing

    CS4525 AUX SERIAL AUDIO I/O PORT SWITCHING SPECIFICATIONS AGND = DGND = PGND = 0 V; T = 25°C; VD = 3.3 V; AUX_SDOUT & DLY_SDOUT C = 15 pF; Inputs: Logic 0 = DGND; Logic 1 = VD; (Note 11)

  • Page 23: Figure 9.Sys_Clk Timing From Reset

    CS4525 XTI SWITCHING SPECIFICATIONS Parameter Symbol Unit External Crystal Operating Frequency ClkFreq[1:0] = ‘00’ 18.240 18.432 18.617 (Note 15) ClkFreq[1:0] = ‘01’ 24.330 24.576 24.822 ClkFreq[1:0] = ‘10’ 26.730 27.000 27.270 XTI Duty Cycle Notes: 15. See “Clock Frequency (ClkFreq[1:0])” on page SYS_CLK SWITCHING SPECIFICATIONS AGND = DGND = PGND = 0 V;...

  • Page 24: Figure 11.Control Port Timing - I²C

    CS4525 I²C CONTROL PORT SWITCHING SPECIFICATIONS AGND = DGND = PGND = 0 V; T = 25°C; VD = 3.3 V; Inputs: Logic 0 = DGND; Logic 1 = VD; SDA C = 30 pF. Parameter Symbol Unit SCL Clock Frequency...
  • Page 25 CS4525 DC ELECTRICAL CHARACTERISTICS AGND = DGND = PGND = 0 V; All voltages with respect to ground; PWM switch rate = 384 kHz; Unless otherwise specified. Parameters Units Normal Operation (Note 17) Power Supply Current VD = 3.3 V Power Dissipation VD = 3.3 V...

  • Page 26: Applications

    6.1.1 System Clocking In software mode, the CS4525 can be clocked by a stable external clock source input on the SYS_CLK pin or by a clock internally generated through the use of its internal oscillator driver circuit in conjunction with an external crystal oscillator. The device automatically selects which of these clocks to use within 10 ms of the release of RST.

  • Page 27: Crystal Oscillator Mode

    SYS_CLK. It should be noted that the internal oscillator driver is disabled when the CS4525 is in reset (RST is low). Any external devices connected to the SYS_CLK output will not receive a clock signal until the CS4525 is taken out of reset.

  • Page 28: Power-Up And Power-Down

    6.1.2 Power-Up and Power-Down The CS4525 will remain in a completely powered-down state with the control port inaccessible until the RST pin is brought high. Once RST is high, the control port will be accessible, but all other internal blocks will remain powered-down until they are powered-up via the control port or until hardware mode is en- tered.

  • Page 29: Input Source Selection

    The serial audio input port digital interface format is configured by the DIF[2:0] bits in the Input Config reg- ister. The CS4525 internal ADC includes a dedicated high-pass filter to remove any DC content from the ADC output signal prior to the internal ADC/serial audio input port input multiplexor. This high-pass filter can be bypassed by clearing the EnAnHPF bit.

  • Page 30: Pre-Scaler

    6.1.4.2 Digital Signal Processing High-Pass Filter The CS4525 includes a high-pass filter at the beginning of the digital signal processing chain to remove any DC content from the input signal prior to the remaining internal digital signal processing blocks. The high-pass filter operates by continuously subtracting a measure of the DC offset from the input signal and may be used regardless of the input data source.

  • Page 31: Emphasis

    6.1.4.4 De-Emphasis The CS4525 includes an on-chip digital de-emphasis filter optimized for a sample rate of 44.1 kHz to ac- commodate audio recordings that utilize 50/15 μs pre-emphasis equalization as a means of noise reduc- tion. The filter response is shown in Figure 15.

  • Page 32: Table 3. Treble Shelving Filter Corner Frequencies

    CS4525 Input Sample Rate Treble Fc 0 Treble Fc 1 Treble Fc 2 Treble Fc 3 32 kHz 5.0 kHz 7.0 kHz 10.0 kHz 15.0 kHz 44.1 kHz 4.8 kHz 6.7 kHz 9.6 kHz 14.4 kHz 48 kHz, 96 kHz 5.2 kHz...

  • Page 33: Parametric Eq

    CS4525 6.1.4.6 Parametric EQ The CS4525 implements 5 fully programmable parametric EQ filters. The filters are implemented in the bi-quad form shown below. x[n] y[n] Figure 16. Bi-Quad Filter Architecture This architecture is represented by the equation shown below where y[n] represents the output sample value and x[n] represents the input sample value.

  • Page 34: Adaptive Loudness Compensation

    6.1.4.7 Adaptive Loudness Compensation The CS4525 includes adaptive loudness compensation to enhance the audibility of program material at low volume levels. The adaptive loudness compensation feature operates by varying the bass and treble boost of the tone control shelving filters as the volume level changes.

  • Page 35: Bass Management

    32 kHz sample rate, and the other is optimized for 44.1 kHz, 48 kHz, and 96 kHz sample rates. The CS4525 automatically detects the input sample rate and chooses the appropriate filter set to apply. The available bass management cross-over frequencies are shown in...

  • Page 36: Volume And Muting Control

    +24 dB to -103 dB in 0.5 dB steps. By default, master vol- ume is set to +3dB; if the CS4525 is being used to control the application’s master volume, then it is recommended to change this value to a comfortable listening level before enabling the PWM powered out- puts.

  • Page 37: 6.1.4.10 Peak Signal Limiter

    CS4525 6.1.4.10 Peak Signal Limiter When enabled, the limiter monitors the digital output following the volume control block, detects when peak levels exceed a selectable maximum threshold level and lowers the volume at a programmable at- tack rate until the signal peaks fall below the maximum threshold. When the signal level falls below a se- lectable minimum threshold, the volume returns to its original level (as determined by the individual and master volume control registers) at a programmable release rate.
  • Page 38 The limiter can be enabled by setting the EnLimiter bit in the Limiter Cfg 1 register The limiter can also be used in conjunction with the thermal limiter function to provide thermal error pro- tection to the CS4525. The thermal limiter function is described in Thermal Limiter...

  • Page 39: 6.1.4.11 Thermal Limiter

    In this state, the peak signal limiter’s operation will follow the EnLimiter, Min[2:0], and Max[2:0] bits with no internal modification. If EnThLim is set again before the CS4525 has been reset (by toggling the RST pin low and then high), thermal limiting will engage immediately.

  • Page 40: 6.1.4.12 Thermal Foldback

    CS4525 6.1.4.12 Thermal Foldback The CS4525 implements comprehensive thermal foldback features to guard against damaging thermal overload conditions. Thermal foldback is similar to the thermal limiting described on page 39 in that both features attenuate the output signal in response to thermal warnings conditions; however, thermal fold- back will attenuate as a function of how long thermal warning has been active whereas thermal limiter always limits by a constant amount.

  • Page 41: 6.1.4.13 2-Way Crossover & Sensitivity Control

    EnTherm bit in the Foldback Cfg register. The CS4525 can be configured to accept an external thermal warning indicator input. When in this con- figuration, an active input signal indicates that a thermal warning threshold has been exceeded. If thermal foldback is enabled, the foldback algorithm will respond as described above making no distinction be- tween an internal or external thermal warning condition.
  • Page 42 CS4525 Input Sample Rate 32 kHz 44.1 kHz 48 kHz, 96 kHz X-Over Freq 5 3.0 kHz 2.88 kHz 3.13 kHz X-Over Freq 6 3.2 kHz 3.07 kHz 3.34 kHz X-Over Freq 7 3.4 kHz 3.26 kHz 3.55 kHz Table 5. 2-Way Cross-Over Frequencies The sensitivity level of the high- and low-pass outputs of the crossovers can be independently adjusted from 0 dB to -7.5 dB in 0.5 dB increments.

  • Page 43: Auxiliary Serial Output

    6.1.5 Auxiliary Serial Output The CS4525 includes a stereo auxiliary serial output which allows an external device to leverage on its internal signal processing and routing capabilities. The auxiliary serial output can receive its data from any of the sources shown in the...

  • Page 44: Serial Audio Delay & Warning Input Port

    The port routes the serial data from the selected input source (the ADC or the serial input port) out to an external serial audio delay device, and then back in to the CS4525 internal dig- ital sound processing blocks. The delay serial audio interface signals include DLY_SDOUT and DLY_SDIN/EX_TWR and are clocked from AUX_LRCK and AUX_SCLK.

  • Page 45: Powered Pwm Outputs

    6.1.7 Powered PWM Outputs The CS4525’s 3 internal modulators can be used to generate multiple powered PWM output configura- tions to enable a wide variety of system implementations. The CS4525 also implements PWM Popguard to minimize output transients in half-bridge configurations.

  • Page 46: Logic-Level Pwm Outputs

    To eliminate power-up pops when used to supply an external PWM amplifier, the CS4525 implements the same click-free start-up function on the PWM_SIG outputs as it does for its own powered PWM outputs.

  • Page 47: Recommended Pwm_Sig Power-Up Sequence For An External Pwm Amplifier

    CS4525 EQ Config register. This bit is active-low and cleared by default. To use the PWM_SIG outputs, the HiZ- PSig bit must be set to enable the PWM_SIG output drivers. 6.1.8.1 Recommended PWM_SIG Power-Up Sequence for an External PWM Amplifier 1.

  • Page 48: Recommended Pwm_Sig Power-Up Sequence For Headphone & Line-Out

    CS4525 6.1.8.3 Recommended PWM_SIG Power-Up Sequence for Headphone & Line- 1. Set the PDnAll bit in the Power Ctrl register to stop the PWM modulators if it is not already set. 2. Configure the PWM_SIG outputs as desired via the PWMDSel[1:0] bits in the Output Cfg register.

  • Page 49: Pwm_Sig Logic-Level Output Configurations

    CS4525 6.1.8.5 PWM_SIG Logic-Level Output Configurations Four channel mapping output configurations are supported for the PWM_SIG output pins as shown in Table 10 below. The configurations support stereo, channel 1 with sub, and channel 2 with sub applica- tions. When disabled, the PWM_SIG pins will continuously drive a logic ‘0’ if the HiZPSig bit is set and will be held in a high-impedance state if the HiZPSig bit is clear.

  • Page 50: Pwm Modulator Configuration

    PWM switching frequency can be easily modified to eliminate interference with AM tuners. 6.1.9.1 PWM Channel Delay The CS4525 includes a PWM output signal delay mechanism. This mechanism allows the PWM switching edges to be offset between channels as a method of managing switching noise and reducing radiated emissions.

  • Page 51: Pwm Am Frequency Shift

    When using a PWM amplifier in a system containing an AM tuner, it is possible that the PWM switch rate conflicts with the desired tuning frequency of the AM tuner. To overcome this effect, the CS4525 includes a PWM switch rate shift feature.

  • Page 52: Table 12. Output Of Pwm_Sig Outputs

    CS4525 HiZPSig HP/Mute HP_DETECT BassMgr [2:0] PWMDSel [1:0] PWM_SIG1 PWM_SIG2 Setting Setting /MUTE Input Setting Setting Output Output High Impedance High Impedance 00 (Disabled) Driven Low Driven Low Channel 1 Channel 2 Channel 1 Mute (Disabled) Channel 2 Mute Not Active...

  • Page 53: 6.1.11 Interrupt Reporting

    PDnAll bit or the PDnOutX bit for the channel in error is set and then cleared. If the AutoRetry bit is set, the CS4525 will attempt to automatically resume power output operation after an over-current error is encountered and before entering the shut-down state. With the AutoRetry function...

  • Page 54: Hardware Mode

    CS4525 Hardware Mode A limited feature set is available when the CS4525 powers up in hardware mode. The available features are described in the following sections. All device configuration is achieved via hardware control input pins. 6.2.1 System Clocking In hardware mode, the CS4525 must be clocked by a stable external clock source input on the SYS_CLK pin.

  • Page 55: Recommended Power-Down Sequence

    6.2.4 PWM Channel Delay In hardware mode, the CS4525 offsets the PWM switching edges between channels as a method of man- aging switching noise and reducing radiated emissions. The OUT3/OUT4 signal pair is delayed from the OUT1/OUT2 signal pair by 4 SYS_CLK cycles as shown Figure 23 below.

  • Page 56: Digital Signal Flow

    6.2.5.1 High-Pass Filter The CS4525 includes a high-pass filter at the beginning of the digital signal processing chain to remove any DC content from the input signal prior to the remaining internal digital signal processing blocks. The high-pass filter operates by continuously subtracting a measure of the DC offset from the input signal; it is always enabled.

  • Page 57: Thermal Foldback

    6.2.6 Thermal Foldback In hardware mode, the CS4525 implements a thermal foldback feature to guard against damaging thermal overload conditions. The thermal foldback feature begins limiting the volume of the digital audio input to the amplifier stage as the junction temperatures rise above the maximum safe operating range specified...

  • Page 58: Automatic Power Stage Shut-Down

    To easily accommodate input sample rates ranging from 32 kHz to 96 kHz without requiring the adjustment of output filter component values, the CS4525 utilizes a sample rate converter (SRC) to keep the PWM switching frequency fixed regardless of the input sample rate. The SRC operates by upsampling the variable input sample rate to a fixed output switching rate, typically 384 kHz for most audio applications.

  • Page 59: Output Filters

    CS4525 Output Filters The filter placed after the PWM outputs can greatly affect the output performance. The filter not only reduces radiated EMI (snubber filter), but also filters high frequency content from the switching output before going to the speaker (low-pass LC filter).

  • Page 60: Full-Bridge Output Filter (Stereo Or Parallel)

    CS4525 6.4.2 Full-Bridge Output Filter (Stereo or Parallel) Figure 27 shows the output filter for a full-bridge configuration. The transient-voltage suppression circuit (snubber circuit) is comprised of a capacitor (680 pF) and a resistor (5.6 Ω, 1/8 W) on each output pin and should be placed as close as possible to the corresponding PWM output pins to greatly reduce radiated EMI.

  • Page 61: Analog Inputs

    0.05 dB of attenuation at 24 kHz, and a DC blocking capacitor to accommodate for the analog input pins’ bias level. The passive attenuator network should be placed as close as possible to the CS4525’s analog input pins to reduce the potential for noise and signal coupling into the analog input traces.

  • Page 62: Serial Audio Interfaces

    CS4525 Serial Audio Interfaces The CS4525 interfaces to external digital audio devices via the serial audio input port and the auxiliary/delay serial ports. The serial audio input port provides support for I²S, Left-Justified and Right-Justified data formats and op- erates in slave mode only, with LRCK and SCLK as inputs. The input LRCK signal must be equal to the sample rate, Fs and must be synchronous to the serial bit clock, SCLK, which is used to sample the data bits.

  • Page 63: Right-Justified Data Format

    Figure 32. Right-Justified Serial Audio Formats Integrated VD Regulator The CS4525 includes two internal linear regulators, one from the VD supply voltage to provide a fixed 2.5 V supply to its internal digital blocks, and another from the VD supply voltage to provide a fixed 2.5 V...

  • Page 64: I²C Control Port Description And Timing

    SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4525 after a Start condition consists of a 7 bit device address field and a R/W bit (high for a read, low for a write).

  • Page 65: Pcb Layout Considerations

    QFN Thermal Pad The CS4525 is available in a compact QFN package. The underside of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground.

  • Page 66: Register Quick Reference

    CS4525 8. REGISTER QUICK REFERENCE This table shows the register names and their associated default values. Name 01h Clock Config EnSysClk DivSysClk ClkFreq1 ClkFreq0 HP/MutePol HP/Mute PhaseShift FreqShift page 69 02h Input Config ADC/SP EnAnHPF Reserved SPRate1 SPRate0 DIF2 DIF1...
  • Page 67 CS4525 Name ..........................MSB-7 BiQuad 2 MSB-8 ..........................LSB+8 B2 Coeff LSB+7 ..................................................MSB-7 BiQuad 3 MSB-8 ..........................LSB+8 A1 Coeff LSB+7 ..................................................MSB-7 BiQuad 3 MSB-8 ..........................LSB+8 A2 Coeff LSB+7 ..................................................MSB-7 BiQuad 3 MSB-8 ..........................
  • Page 68 CS4525 Name 55h Volume Cfg SZCMode1 SZCMode0 Mute50/50 AutoMute En2Way 2WayFreq2 2WayFreq1 2WayFreq0 page 80 56h Sensitivity LowPass3 LowPass2 LowPass1 LowPass0 HighPass3 HighPass2 HighPass1 HighPass0 page 81 57h Master Vol MVol7 MVol6 MVol5 MVol4 MVol3 MVol2 MVol1 MVol0 page 82...

  • Page 69: Register Descriptions

    CS4525 9. REGISTER DESCRIPTIONS All registers are read/write unless otherwise stated. All “Reserved” bits must maintain their default state. Clock Configuration (Address 01h) EnSysClk DivSysClk ClkFreq1 ClkFreq0 HP/MutePol HP/Mute PhaseShift FreqShift 9.1.1 SYS_CLK Output Enable (EnSysClk) Default = 1 Function: This bit controls the output driver for the SYS_CLK signal.

  • Page 70: Hp_Detect/Mute Pin Active Logic Level (Hp/Mutepol)

    CS4525 9.1.4 HP_Detect/Mute Pin Active Logic Level (HP/MutePol) Default = 0 Function: This bit determines the active logic level for the HP_DETECT/MUTE input signal. HP/MutePol Setting Headphone Detect/Mute Input Polarity 0 .......... Active low. 1 .......... Active high. 9.1.5 HP_Detect/Mute Pin Mode (HP/Mute)

  • Page 71: Input Configuration (Address 02H)

    CS4525 Input Configuration (Address 02h) ADC/SP EnAnHPF Reserved SPRate1 SPRate0 DIF2 DIF1 DIF0 9.2.1 Input Source Selection (ADC/SP) Default = 0 Function: This bit selects the audio input source. ADC/SP Setting Audio Input Source 0 ..........Digital input from the serial audio input port.

  • Page 72: Aux Port Configuration (Address 03H)

    CS4525 AUX Port Configuration (Address 03h) EnAuxPort DlyPortCfg1 DlyPortCfg0 AuxI²S/LJ RChDSel1 RChDSel0 LChDSel1 LChDSel0 9.3.1 Enable Aux Serial Port (EnAuxPort) Default = 0 Function: Controls the operation of the auxiliary serial port. EnAuxPort Setting Auxiliary Port State 0 .......... Auxiliary port disabled.

  • Page 73: Aux Serial Port Left Channel Data Select (Lchdsel[1:0])

    CS4525 9.3.5 Aux Serial Port Left Channel Data Select (LChDSel[1:0]) Default = 00 Function: Selects the data to be sent over the left channel of the auxiliary port serial data output signal. LChDSel[1:0] Setting Aux Serial Port Left Channel Output Data Source 00 ........Channel A.

  • Page 74: Foldback And Ramp Configuration (Address 05H)

    CS4525 only be changed while all modulators and associated logic are in the power-down state (the PDnAll bit is set). Attempts to write these bits while the PDnAll bit is cleared will be ignored. See “PWM Channel Delay” on page 55 for more information.

  • Page 75: Foldback Attack Delay (Attackdly[1:0])

    CS4525 9.5.4 Foldback Attack Delay (AttackDly[1:0]) Default = 01 Function: Controls the foldback attack delay. See “Thermal Foldback” on page 40 for more information. AttackDly[1:0] Setting Foldback Attack Time 00 ........Approximately 0.5 seconds. 01 ........Approximately 1.0 seconds. 10 ........Approximately 1.5 seconds.

  • Page 76: Right Channel Mixer (Rchmix[1:0])

    CS4525 9.6.2 Right Channel Mixer (RChMix[1:0]) Default = 00 Function: Controls the right channel mixer output. See “Channel Mixer” on page 30 for more information. RChMix[1:0] Setting Right Channel Mixer Output on Channel B 00 ........Right Channel 01 ........(Left Channel + Right Channel) / 2 10 ........

  • Page 77: Digital Signal Processing High-Pass Filter (Endighpf)

    CS4525 9.7.3 Digital Signal Processing High-Pass Filter (EnDigHPF) Default = 0 Function: Controls the operation of the digital signal processing high-pass filter. See “Digital Signal Processing High-Pass Filter” on page 30 for more information. EnDigHPF Setting Digital Signal Processing High-Pass Filter State 0 ..........Digital signal processing high-pass filter disabled.

  • Page 78: Tone Control (Address 08H)

    CS4525 Tone Control (Address 08h) Treble3 Treble2 Treble1 Treble0 Bass3 Bass2 Bass1 Bass0 9.8.1 Treble Gain Level (Treb[3:0]) Default = 1000 Function: Sets the gain/attenuation level of the treble shelving filter.The level can be adjusted in 1.5 dB steps from +12.0 to -10.5 dB.

  • Page 79: Hi-Z Pwm_Sig Outputs (Hizpsig)

    CS4525 9.9.2 Hi-Z PWM_SIG Outputs (HiZPSig) Default = 0 Function: When cleared, the PWM_SIG1 and PWM_SIG2 output drivers are placed in a high-impedance state. When set, the PWM_SIG1 and PWM_SIG2 output drivers are active. It should be noted that the function of the PWM_SIG outputs is determined by the PWMDSel[1:0] bits in Register 04h.

  • Page 80: Volume And 2-Way Cross-Over Configuration (Address 55H)

    Default = 1 Function: When enabled, the outputs of the CS4525 will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. See “Volume and Muting Control”...

  • Page 81: Enable 2-Way Crossover (En2Way)

    CS4525 9.10.4 Enable 2-Way Crossover (En2Way) Default = 0 Function: Enables the 2-way crossover filters for channel 1 and channel 2. En2Way Setting 2-Way Crossover State 0 ..........2-way crossover disabled. 1 ..........2-way crossover enabled. 9.10.5 2-Way Cross-Over Frequency (2WayFreq[2:0]) Default = 000 Function: Selects the cross-over frequency for the 2-Way Linkwitz-Riley filters.

  • Page 82: Channel A And Channel B High-Pass Sensitivity Adjust (Highpass[3:0])

    CS4525 9.11.2 Channel A and Channel B High-Pass Sensitivity Adjust (HighPass[3:0]) Default = 0000 Function: Controls the 2-way cross-over high-pass sensitivity adjustment. See “2-Way Crossover & Sensitivity Con- trol” on page 41 for more information. HighPass[3:0] Setting Sensitivity Compensation Level 0000 ........

  • Page 83: Channel A And B Volume Control (Address 58H & 59H)

    CS4525 9.13 Channel A and B Volume Control (Address 58h & 59h) ChXVol7 ChXVol6 ChXVol5 ChXVol4 ChXVol3 ChXVol2 ChXVol1 ChXVol0 9.13.1 Channel X Volume Control (ChXVol[7:0]) Default = 30h Function: Sets the gain/attenuation levels of channel A and channel B. See “Volume and Muting Control”...

  • Page 84: Mute/Invert Control (Address 5Bh)

    CS4525 9.15 Mute/Invert Control (Address 5Bh) InvADC InvSub InvCh2 InvCh1 MuteADC MuteSub MuteChB MuteChA 9.15.1 ADC Invert Signal Polarity (InvADC) Default = 0 Function: When set, the signal polarity of the ADC will be inverted. InvADC Setting ADC Signal Inversion State 0 ..........

  • Page 85: Sub Channel Mute (Mutesub)

    CS4525 function is affected, similar to attenuation changes, by the soft and zero cross bits (SZCMode[1:0]). See “Volume and Muting Control” on page 36 for more information. MuteChX Setting Channel X PWM Mute State 0 ..........Channel X PWM outputs un-muted.

  • Page 86: Peak Signal Limit All Channels (Limitall)

    CS4525 9.16.3 Peak Signal Limit All Channels (LimitAll) Default = 1 Function: When cleared, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the specific channel indicating clipping. The other channels will not be affected. When set, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on all channels in response to any single channel indicating clipping.

  • Page 87: Limiter Configuration 2 (Address 5Dh)

    CS4525 9.17 Limiter Configuration 2 (Address 5Dh) Reserved Reserved RRate5 RRate4 RRate3 RRate2 RRate1 RRate0 9.17.1 Limiter Release Rate (RRate[5:0]) Default = 111111 Function: Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in the limiter threshold register.

  • Page 88: Power Control (Address 5Fh)

    Shut-Down” on page WARNING: The EnOCProt bit must never to changed from its default value of 1. Doing so will disable the over-cur- rent protection feature and may result in permanent damage to the CS4525. 9.19.3 Select VD Level (SelectVD)

  • Page 89: Power Down (Pdnall)

    Default = 1 Function: The CS4525 will enter a power-down state when this function is enabled: 1. The power PWM outputs will be held in a high-impedance state. 2. The logic-level PWM outputs will continuously drive a logic ‘0’ if the HiZPSig bit is set and will be held in a high-impedance state if the HiZPSig bit is clear.

  • Page 90: Adc Overflow Interrupt (Adcovfl)

    9.20.2 ADC Overflow Interrupt (ADCOvfl) Function: This bit is read only. When set, indicates that an over-range condition occurred anywhere in the CS4525 ADC signal path and has been clipped to positive or negative full scale as appropriate since the last read of this register.

  • Page 91: Mask For Src State (Srclockm)

    CS4525 If this bit is set, indicating an amplifier stage error condition, and the AmpErrM bit is set to a ‘1’b, the INT pin will go active. To determine the actual current state of the amplifier error condition, read the amplifier error status register.

  • Page 92: Mask For Amplifier Error (Amperrm)

    This bit is read only and will identify the presence of an overflow condition within the ADC. When set, in- dicates that an over-range condition is currently occurring in the CS4525 ADC signal path and has been clipped to positive or negative full scale.

  • Page 93: Channel X Overflow (Chxovflst)

    CS4525 9.21.4 Channel X Overflow (ChXOvflSt) Function: These bits are read only and will identify the presence of an overflow condition anywhere in the associated channel’s signal path. When set, indicates that an over-range condition is currently occurring in the chan- nel’s signal path and has been clipped to positive or negative full scale.

  • Page 94: Under Voltage / Thermal Error State (Uvte[1:0])

    DeviceID1 DeviceID0 RevID2 RevID1 RevID0 9.23.1 Device Identification (DeviceID[4:0]) Default =11111 Function: Identification code for the CS4525. DeviceID[4:0] Setting Device ID Notes 11111........Permanent device identification code. 9.23.2 Device Revision (RevID[2:0]) Function: Identifies the CS4525 device revision. RevID[2:0] Setting Device Revision 000 ........

  • Page 95: 10.Parameter Definitions

    Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. 11.REFERENCES 1. Cirrus Logic, “AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,” Version 6.0, February 1998. 2. Cirrus Logic, “AN22: Overview of Digital Audio Interface Data Structures, Version 2.0”, February 1998.; A useful tutorial on digital audio specifications.

  • Page 96: 12.Package Dimensions

    CS4525 12.PACKAGE DIMENSIONS 48L QFN (9 × 9 MM BODY) PACKAGE DRAWING Pin #1 ID Pin #1 ID Top View Side View Bottom View INCHES MILLIMETERS NOTE 0.0354 0.90 0.0000 0.0020 0.00 0.05 0.0118 0.0138 0.0157 0.30 0.35 0.40 0.3543 BSC 9.00 BSC...

  • Page 97: 13.Thermal Characteristics

    (and inner ground layer, if applicable) of the PCB. In either case, it is beneficial to use copper fill in any unused regions inside the PCB layout, especially those immediately surrounding the CS4525. In addition to improving in electrical performance, this practice also aids in heat dissipation.

  • Page 98: 15.Revision History

    TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

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