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7. Circuit Descriptions
Index of this chapter:
7.1 Introduction
7.2 The various circuits
7.1
Introduction
The SK4.1L CA is a CRT TV based on the 3P62 platform. In
this chapter, only a general description of the various circuits is
given. For more detailed information, see the circuit diagrams
in this manual.
7.1.1
Main Board Diversity
It should be noted that the main board of sets with a 21SL9
styling differs slightly from the main board of the (older) SL7
sets. The differences are depicted in
between set type and -style, refer to
Table 7-1 Delta's 21SL9 versus SL7 sets
Position
SL7
R629
1 k
R326
-
R417
-
D614
RU4AM
ZD603
3.6 V
7.2
The various circuits
7.2.1
Tuner
The function of the tuner is to select the channel to be received
and suppress the interference of neighboring channels, to
amplify the high frequency signal, to improve the receiving
sensitivity and SNR, and to generate a PIF signal through
frequency conversion.
7.2.2
IF Channel
The IF Channel mainly ensures the sensitivity and selectivity of
the complete TV set. The IF AMP integrated in the UOCIII is
made up of a three-stage dual-differential amplifier with a gain
value above 70 dB, a SNR of 55 dB and a bandwidth of 7 MHz.
The video demodulation circuit is made from the built-in PLL
Sync Detector. The spectrum of the demodulation carrier is
unitary and it is not affected by the content of the video signal.
The tuner features stable receptivity while the signal output
from the video detector features high fidelity. The built-in PLL
circuit of the UOCIII generates a 38.0 MHz or 38.9 MHz
demodulation reference signal for the sync detector to
demodulate the video signal; this is called "PLL sync
demodulation".
7.2.3
Sound Channel
An external ceramic filter is used to select the second SIF
signal for the sound channel of UOCIII from the signal output of
the video detector. The audio signal is obtained after limiting
amplification and demodulation by the intermediate frequency
detector for the SIF signal, and then the audio signal is fed to
the BTSC stereo/SAP decoder TDA9850. From that it is output
to the audio amplifier TFA9842, which drives the speakers to
provide the sound. The intermediate frequency detector and
volume-control attenuator that are built in the UOCIII are set
and adjusted via the CPU.
Circuit Descriptions
Table
7-1. For the relation
Table
2-1.
21SL9
2.2 k
added
added (10 k)
RU3AM
4.3 V
SK4.1L CA
7.2.4
BTSC stereo/SAP decoder
Input Level Adjustment
The composite input signal is fed to the input level adjustment
stage. The control range is from -3.5 to +4.0 dB in steps of
0.5 dB. The maximum input signal voltage is 2 V (RMS).
Stereo Decoder
The output signal of the level adjustment stage is coupled to a
low-pass filter which suppresses the baseband noise above
125 kHz. The composite signal is then fed into a pilot detector/
pilot cancellation circuit and into the MPX demodulator. The
main L + R signal passes a 75 ms fixed de-emphasis filter and
is fed into the dematrix circuit. The decoded sub-signal L - R is
sent to the stereo/SAP switch. To generate the pilot signal the
stereo demodulator uses a PLL circuit including a ceramic
resonator. The stereo channel separation is adjusted by an
automatic procedure to be performed during set production.
The stereo identification can be read by the I
different pilot thresholds (data STS = 1; STS = 0) can be
2
selected via the I
C-bus.
SAP Demodulator
The composite signal is fed from the output of the input level
adjustment stage to the SAP demodulator circuit through a 5fH
band-pass filter. The demodulator level is automatically
controlled. The SAP demodulator includes an internal field
strength detector that mutes the SAP output in the event of
insufficient signal conditions. The SAP identification signal can
2
be read by the I
C-bus.
Noise Detector
The composite input noise increases with decreasing antenna
signal. This makes it necessary to switch stereo or SAP off at
certain thresholds. These thresholds can be set via the I
bus. With ST0 to ST3 the stereo threshold can be selected and
with SP0 to SP3 the SAP threshold. A hysteresis can be
achieved via software by making the threshold dependent of
the identification bits STP and SAPP.
Mode Selection
The stereo/SAP switch feeds either the L - R signal or the SAP
demodulator output signal via the internal dbx noise reduction
circuit to the dematrix/switching circuit. Different switch modes
provided at the output pins OUTR and OUTL are available.
dbx Decoder
The dbx circuit includes all blocks required for the noise
reduction system in accordance with the BTSC system
specification. The output signal is fed through a 73 ms fixed de-
emphasis circuit to the dematrix block.
SAP Output
Independent of the stereo/SAP switch, the SAP signal is also
available at pin SAP. At SAP, the SAP signal is not dbx
decoded. The capacitor at SDE provides a recommended de-
emphasis (150 ms) at SAP.
Integrated Filters
The filter functions necessary for stereo and SAP demodulation
and part of the dbx filter circuits are provided on-chip using
transconductor circuits. The required filter accuracy is attained
by an automatic filter alignment circuit.
7.2.5
CRT Drive Circuit
In the driver circuit, both the voltage and current of the R/G/B
signal are amplified, after which the CRT drive circuit
modulates the cathode beam current of the CRT. The R/G/B
signal input into the driver circuit is of negative polarity.
7.
EN 15
2
C-bus. Two
2
C-
2009-Jul-24
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