Table of Contents
Advertisement
LF
MUL
TlPLlER 11-1255
Principle
4.71
Freguency multipl ication is achieved by a vol tage controlled osci I1 ator which is
set to run at 100 times the input frequency.
The oscillator control is derived from
phase comparison of the frequency divided output of the oscillator with the incoming
frequency.
Circuit Description (Fig. 6)
4.72
The LF signal is fed to the p.c.b. at pin 2, and passes via Cl to IC1/2.
ICl
is an operational ampl ifier having feedback which gives Schmitt trigger
characteristics.
An
input of 400 mV peak to peak will give an output of approximately 6V
peak to peak.
4.73
IC2 contains a voltage controlled oscillator operating in a phase locked loop.
The output of ICl is fed to one of the phase comparator inputs 1C2/14. The
oscillator frequency is controlled by:
(1)
The vol tage at IC2/9.
(2)
The resistance from IC2/11 to the negative rail.
(3)
The capacitance between IC2/6 and IC2/7.
(4)
The phase comparator output at IC2/13.
4.74
The oscillator output at IC2/4 is fed via Q3 to a dual decade divider, IC3.
From IC3/13 the divided signal is fed back via Q2 to the second phase
comparator input IC2/3. The phase comparator output at IC2/13 is fed to the oscillator
control connection IC2/9, and results in the oscillator running at a precise multiple of the
input frequency.
4.75
The division ratio required in IC3 is 100. This is set by the fitting of Iink LK2.
When fitting a new LF multiplier p.c.b. ensure that LK2 is fitted between pins
3 and 4 of IC3 and that LK1 is not fitted.
4-13
9916 Vol. 2
Hide quick links:
Advertisement
Table of Contents
