Panasonic DMR-E53EG Service Manual page 281

C3914 C3915 C3916
50V1 50V1 50V1
38 37 36 35 34
EXTEMAL
CONTROL4
A
B
LPF BUF
C
MUTE
AUDIO
SWITCH Lch
A
B
Lch
BUF C
D
MUTE
A
B
BUF
LPF
C
EXT MUTE CONTROL
MUTE
(HLCH
OPEN LOW
POWER SAVE
(HLCH SW3B)
OPEN LOW NORMAL1
TL
TO
AUDIO
VIDEO SW3
VCC
CLAMP
R L
7 8 9 10 11
C3930 R3911 R3912 C3931 C3932
.01 2200 2200 50V1 50V1
R3985
700
R3910
50
B5 B12 B13
6 7
66
C3920
0.1
C3921
6V330
C3918 C3919
16V10 16V10
C3917 R3980 R3979
50V1 470 470
33 32 31 30 29
ALWAYS VCC
(5V+0.5V)
-
GAIN CTL
(0,2,4,6dB)
AMP AMP
OR
SW3B)
NORMAL1
10V REG
TO
REF
VCC 12V DC
CLAMP
(12V+0.5V)
-
12 13 14 15 16
C3933 C3934
16V100 0.01
C3935
16V100
R3913
180
R3986
1200
B6 B14 B15
8
A4
C3923
0.1
C3924
6V330
C3922
0.01
28 27 26 25 24
CLAMP
75 75 CONTROL VCC
DR DR (5V+0.5V)
-
LPF LPF
6dB 6dB
AMP AMP
A
B
C
MUTE
SERIAL VIDEO
CONTROL SWITCH
A
B
C
D
MUTE
A
B
C
MUTE
FSS CONTROL
TERMINAL
100K (L.M.H)
BLANKING
(L)
DATA CLOCK
EXTEMAL
INTERFACE
100K
CLAMP CONTROL3
BLOCK
SDA
17 18 19 20 21
C3939 R3975
0.01 100
C3938
0.1
B3 B2
9
<BOOSTER+5V>
<PS+5V>
C3925
0.01
23
CLAMP
SCL
22
R3976
100
<PS+5V>
<PS+12V>
B1
DMR-E53EG,E55EB/EG/EBL/EP
Scart Schematic Diagram
10
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
11