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Avago ACPL-P346 User Manual

Isolated power mosfet gate driver evaluation board

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ACPL-P346/W346
Isolated Power MOSFET Gate Driver Evaluation Board
User's Manual
Quick Start
Visual inspection is needed to ensure that the evaluation board is received in good condition.
All part references are designated with suffix 'a' and 'b' to indicate the lower and the upper inverter arms, respectively. If
part references are made without suffixes, then they are valid for both upper and lower inverter arms (except R6, which
is shared).
Figure 1 shows the default connections of the evaluation board:
1. Q1 and Q2 are not mounted. Actual Power MOSFET can be mounted at either Q1 (for TO-220 package) or Q2 (for TO-
247 package) or connected to the driver board through short wire connections from the holes provided at Q1 or Q2.
2. D4 and R7 are not mounted (on solder side). A 12 V Zener diode footprint at D4 is provided to allow for a single DC
power supply of 15 V ~25 V to be applied across V
Q2) can then be generated and it acts as the reference point at the source pin of each power MOSFET. V
stay at 12 V above the virtual ground V
3. S2 and S3 jumpers are shorted by default to connect V
If a negative supply is needed, then S2 and S3 jumpers must be removed.
4. Bootstrap diode D3b and resistor R6 are connected by default. These two components are provided to help generate
V
supply through bootstrapping assuming that V
CC2b
only when Q1 or Q2 are mounted in a half-bridge configuration and turned on and off through proper PWM driving
signals.
5. S1 is shorted by default to ground the IN- (or LED-, the cathode of LED) pin when V
removed if IN- cannot be grounded.
6. Upper and lower arms of the inverter will have common V
connected by solder between upper and lower inverter PCB portions (and GND1 on the solder side).
7. Provisions are also made to allow V
this DC/DC converter is used, S2, S3 (and R6) should be disconnected.
V
CC1b
V
CC1a
Figure 1. Actual ACPL-P346/W346 evaluation board showing default connections
. R7 is needed to generate the bias current across D4.
E
(and V
CC2
EE
S1 (shorted)
S2 (shorted)
and V
if needed. A virtual ground V
CC2
EE
to V
, assuming that a negative supply is not needed. Note:
E
EE
supply is available. Note: Bootstrapping supply works
CC2a
(and GND1), a provision is made to allow V
CC1
) to be generated from V
S3 on solder side (also shorted)
(at Source pin of Q1 or
E
is supplied. This short can be
CC1
through a DC/DC converter at IC2. When
CC1
will then
CC2
to be
CC1

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Summary of Contents for Avago ACPL-P346

  • Page 1 DC/DC converter at IC2. When this DC/DC converter is used, S2, S3 (and R6) should be disconnected. CC1b CC1a S3 on solder side (also shorted) S1 (shorted) S2 (shorted) Figure 1. Actual ACPL-P346/W346 evaluation board showing default connections...
  • Page 2 D3b and R6. c. V representing the output voltage of ACPL-P346/W346 (IC1a) at the gate pin of Q1a (or Q2a) w.r.t. V d. V (through an isolated probe) representing the output voltage of ACPL-P346/W346 (IC1b) at the gate pin of Q1b (or Q2b) w.r.t.
  • Page 3 10 µF T GNDb IC1a CC2a CON1a ACPL-P346 249R LEDa+ 0.1 µF TP1a 4R7 1W TO220/TO247 SS32 S Q1a/Q2a 130R LEDa- IC2a BYM26F CC2a TP2a CC1a TP3a R05P212D/R8 10µF T TP4a GNDa 10µF T Figure 3. Schematics of ACPL-P346/W346 evaluation board...
  • Page 4 Practical connections of the evaluation board using a power MOSFET for an actual inverter test 1. Solder actual power MOSFETs at Q1 (or Q2) for the top and bottom arms of the half-bridge inverter isolated drivers. 2. Connect a +5V DC isolated supply1 across +5V and GND terminals of CON1 for both arms of the isolated drivers. 3.
  • Page 5 Application Circuit Description The ACPL-P346/ACPL-W346 is an isolated gate driver that provides 2.5 A output current. The voltage and high peak output current supplied by this optocoupler make it ideally suited for direct driving of MOSFET with ratings up to 1000 V/100 W.
  • Page 6 S3 jumpers are shorted by default but this has no effect on actual operation of the board. Contact Avago Technologies if bootstrapping operation works are required. 2. Scheme 2 is similar to Scheme 1: it has V and V supplies.
  • Page 7 Table 1. Power Supply Schemes D4a/ D4b/ R7b Remarks cc2a cc2b +5 V +12V~20V Bootstrapped Default (simplest) External External from V - Two external supplies needed cc2a (+12V~20V) for V and V cc2a +5 V +12V~20V +12V~20V Higher Power External External External - Three external supplies needed...
  • Page 8: Output Measurement

    Output Measurement A sample of input LED and various output waveforms are captured and shown in Figure 6. The default setup connection is adopted, except with Q1a and Q1b power MOSFETs are mounted. The power MOSFETs used have a gate capacitance equivalent to 10 nF.
  • Page 9 For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.

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Acpl-w346