IBM 3745 Maintenance Information Reference page 256

Before the swap
Physical Addresses
1 2 3 4 5 6 7
DMUX LIC LIC LIC LIC LIC LIC LIC LIC
Card
A B
C
0 E F G H
Logical Addresses
1
2
3 4
5 6
7
After the swap
Physical Addresses
1 2
3
4 5 6 7
DMUX
LIC
LIC
LIC
LIC
LIC
LIC
LIC LIC
Card
A B
C
0 E F G H
Logical Addresses
'7 ' 1 2
3
4 5 6 '0 '
After the swap, on the serial link, LlCA takes the slots of LlCH and LlCH takes
the slots of LlCA.
LIC Address Register Contents
In Write Mode In Read Mode
Bits'
Meanings Bits Meanings
0 LlC logical address bit 0 0 LlC wired address bit 0
1 LlC logical address bit 1 1 LlC wired address bit 1
2 LlC logical address bit 2 2 LlC wired address bit 2
3 Enable/disable logical add 3 (Not used)
4 (Not used)
4
EC number
5 (Not used)
5 EC number
LIC Control Register
The LlC control register X'02' bits 1 and 3 (line enable EO and E1) control the
swapping.
Bits Meaning
0 High-speed line
1 Line enable EO
2 X.21 CCITT used by FESA 80
3 Line enable E1
4 (Not used)
5 Transmit bit echo
Enable Clock Mode
Register X'03' bits 4 and 5 select the clock mode. They are OFF after a reset
command (that is 00
=
diag mode).
There is no clock until the enable clock mode bit is set, except if the LlC detects
that the cable ID is a local attach cable. After the reset the LlC forces the local
attach clock mode: 11 (speed given by ICF after reset: 2400 bps).
Chapter 4. Transmission Subsystem (TSS)
4-53