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Printed-Circuit Board Layout Guideline
Load
#1
USB
Cable
3. Turn on PS#1 output.
4. Software setup: Change Operation Mode to Boost Mode.
Measure → V(J1(DC+, DC–)) = 5 V ±0.2 V
5. Enable Load #1.
Measure → V(J1(DC+, DC–)) = 5 V ±0.2 V
Measure → Iin = 330 mA ±40 mA
Measure → Io = 200 mA ±20 mA
3
Printed-Circuit Board Layout Guideline
1. To obtain optimal performance, the power input capacitors, connected from input to PGND, must be
placed as close as possible to the integrated circuit (IC).
2. The output inductor must be placed close to the IC and the output capacitor connected between the
inductor and PGND of the IC. The intent is to minimize the current path loop area from the SW pin
through the LC filter and back to the PGND pin. To prevent high-frequency oscillation problems, proper
layout to minimize high-frequency current path loop is critical.
3. The sense resistor must be adjacent to the junction of the inductor and output capacitor. Route the
sense leads connected across the RSNS back to the IC, close to each other (minimize loop area) or
on top of each other on adjacent layers (do not route the sense leads through a high-current path).
4. Place all decoupling capacitors close to their respective IC pin and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals must be routed
away from the high current paths.
5. The PCB must have a ground plane (return) connected directly to the return of all components through
vias (two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per
capacitor for small-signal components). A star ground design approach is typically used to keep circuit
block currents isolated (high-power/low-power small-signal) which reduces noise-coupling and ground-
bounce issues. A single ground plane for this design gives good results. No ground-bounce issue
occurs with this small layout and a single ground plane. Having the components segregated minimizes
coupling between signals.
6. The high-current charge paths into VBUS, PMID, and from the SW pins must be sized appropriately for
the maximum charge current in order to avoid voltage drops in these traces. The PGND pins must be
connected to the ground plane to return current through the internal low-side FET.
8
bq24153A/56A/57/58/59 Fully Integrated, Switch-Mode, One-Cell, Li-Ion
Charger With Full USB Compliance and USB-OTG Support EVM
BQ2415x
EVM
J 1
I
Io
APPLICATION
DC+
V
DC -
JMP1
D1
Ribbon
HPA172
Cable
J5
J3
Figure 4. Boost Function Test Setup
Copyright © 2010–2013, Texas Instruments Incorporated
J2
BAT+
JMP3
U1
AUXPWR
CD
BAT -
JMP5
CIRCUIT
JMP2
JMP4
J4
SLUU453C – November 2010 – Revised May 2013
www.ti.com
I in
I
Power
V
supply #1
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