Advertisement
The heart of this unit is the circuitry based around U10b (pins 5, 6, 7). This, along with the
'up' and 'down' pots, make up the lag generator. What is a lag generator? Basically it is a
capacitor, C37 in this circuit, that can discharged and charged at a controlled rate. The level to
which the capacitor charges to, or discharges to, is determined by the input voltage applied to
pin 5 of U10. The voltage across the capacitor will directly control the output of the envelope
processor.
U12 is an analogue switch. It is a good old 4016, and this IC is found in hundreds of synth
circuits. In the Filtrex, it doesn't do a great deal other than select which mode the envelope
processor is going to be in. The 4016 is controlled by the 'mode' switch. For the envelope
processor to be in envelope follower, or EF, mode, the FWR output needs to be patched into
the lag generator. U12 (pins 6, 8, 9) switches on, and U12 (pins 10, 11, 12) is off. The
positive voltage that is being produced by the FWR will now start to charge or discharge C37
up and down. The speed of the charging will be controlled by the 'up' pot, and the speed of
the discharge will be controlled by the 'down' pot. U10c (pins 8, 9, 10) buffers the voltage
across C37 to create the positive going EF output signal. U10d (pins 12, 13, 14) inverts this to
produce negative going voltages. The 'envelope' pot controls the depth of the effect. The
position of the pot's wiper will determine the polarity and the level of the final output signal.
D3 and 4, along with R58, create a dead band around zero volts so the pot doesn't have to be
exactly in the middle for no modulation.
In EG mode, U12 is switched over to allow the output of the EG logic circuity to control the
lag generator. The output of this logic circuitry is either high, +7.5V or low, 0V. The logic
circuitry can operate in two modes, attack-decay (AD) or attack-release (AR).
Several sources can initiate the attack phase. One is the external 'gate' signal. This is a switch
type signal that is either at around 0 volts when off, or any positive voltage greater than 3V
when on. The Filtrex can easily handle greater voltages, within reason, without damage. D5
protects Q11 from any negative inputs.
Other sources of triggering the attack phase come from the LFO and the threshold detector
already discussed in this document. Both of these trigger the unit by pulling the collector of
Q11 down to zero via the TRIG bus.
When a positive gate signal arrives, Q11 turns on and pulls its collector down to ground or
0V. This inverse version of the applied gate signal is sent to two destinations. One is another
transistor, Q14. This is configured as another inverter. Thus the output of Q14 produces a
copy of the gate signal that swings from 0 when off to +15V when on. R86 passes some
current back to the first transistor. This creates a type of Schmitt trigger action which makes
the transistors change state faster. It therefore allows slowly varying signals to trigger the
Filtrex. For example you can use a slow sine wave or aftertouch CV to fire the EG.
The output of Q14 is passed on to a CR network that acts as a differentiator. This circuit
produces a positive voltage spike when the gate goes high. The duration of the spike is
determined principally by the values of C43 and R93. D12 prevents a negative spike being
produced when the gate goes low. The positive spike triggers an RS flip-flop circuit based
around two NOR gates, U13.
12
Advertisement
