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4.12
BW/CVF SCHEMATIC DIAGRAM [GR-AX970U]
TO DSP
BWBLEVEL
TO REG
5
REG_3.2V
R7337
0
SCK3
TO CPU
R7338
0
VF_CS
SO3
CN11
CVF_SO3
TO C-VF
CVF_SCK3
CN7701
CVF_CS
4
GND
TO REG
REG+12V
TO CPU
VF_CTL
R7334
TO REG
REG_4.8V
TO CPU
V_PLS_ON
R7335
For PANA MODEL
CN9025
Q7308
GND
3
BWVFADJ
VDCVF
TO DSP
HDCVF
CN25
BWVFADJ
JIG CONN.
GND
BWYGAIN
TO DSP
BWYOUT
CN12
OPEN
2
BW_VF_Y
GND
VF_BL4.8
C7326
∗
∗
∗
R7330
Q7310
∗
∗
R7332
∗
1
R7333
∗
C7325
∗
T
Q7311
NOTE : The parts with marked ( ) is not used.
A
B
∗
IC7302
∗
NC
D7301
NC
VDDH
C7318
TEST
L7302
SEL_PDR
VBAT
C7321
∗
∗
A_VBAT
H_SYNC
V_SYNC
VHIO_SEL
∗
R7301
∗
∗
R7302
∗
R7309
∗
∗
∗
Q7301
∗
R7327
∗
∗
Q7306
∗
∗
Q7307
∗
∗
∗
C
D
NOTES :
For the destination of each signal and further line connections that are cut off from
this diagram , refer to "4.1 BOARD INTERCONNECTIONS".
When ordering parts , be sure to order according to the Part Number indicated in the Parts List.
Q7303
UMD3N-W
∗
Q7304
PUMX1-W
C7312
∗
∗
HPL
V_REF
VSS
IC7301
VDD
∗
VEE
V_COM
HODL
VPL
VCK
VIDH
∗
∗
∗
R7313
∗
∗
R7306
∗
∗
∗
∗
∗
∗
∗
GAIN
E
4-25
4-26
∗
Q7305
∗
∗
C7311
∗
C7310
∗
C7309
∗
C7308
∗
0 1 MAIN (BW/CVF)
M2_MAIN_BW/CVF_BLOCK
JVC_CVF_MODEL
y30170001a_rev0
F
G
TO C-VF BL
CN7801
CN11
VF_BLK
REG_4.8V
CN9012
∗
GND
BWVFADJ
RENON
RENEN
HCLKN
HPLN
VF_BLK
VREF
GND
BW_VDD
REG_4.8V
BW_VEE
BW_COM
HLTOR
HODL
VPLN
VCKN
VIDHI
PDR
GND
For PANA MODEL
H
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