Aiwa CSD-ED79 Service Manual page 21

IC, LA9241ML
Pin No. Pin Name I/O
Connected to pickup photo-diode. Adding with FIN1 pin generates RF signal, and
1 FIN2 I
subtracting from FIN1 generates FE signal.
2 FIN1 I Connected to pickup photo-diode.
3 E I Connected to pickup photo-diode. Subtracting from F pin generates TE signal.
4 F I Connected to pickup photo-diode.
5 TB I Input DC components of TE signal.
6 TE– O Connected to TE pin with resistor set TE signal gain.
7 TE O Output TE signal.
8 TESI I Input TES (TRACK ERROR SENSE) comparator. Band pass and input TE signal.
9 SCI I Input shock detection.
10 TH I Establish tracking gain value.
11 TA O TA amplifier output.
12 TD– I Compose tracking phase compensation value between TD and VR pins.
13 TD O Used for tracking phase compensation setting.
14 JP I Establish amplitude of tracking jump signal (kick pulse).
15 TO O Output tracking control signal.
16 FD O Output focusing control signal.
17 FD– I Compose focusing phase compensation value between FD and FA pins.
18 FA O Compose focusing phase compensation value between FD– and FA– pins.
19 FA– I Compose focusing phase compensation value between FA and FE pins.
20 FE O Output FE signal.
21 FE– I Connected to FE pin with resistor set FE signal gain.
22 AGND – Analog GND.
23 SP O Output single-end for CV+ and CV– pins input signal.
24 SPI I Spindle amplifier input.
25 SPG I Connect resistor for gain setting at spindle 12cm mode. (Not used)
26 SP– I Connect spindle phase compensation value with SPD pin.
27 SPD O Output spindle control signal.
28 SLEQ I Connect sled phase compensation value.
29 SLD O Output sled control signal.
30 SL–
I Input sled sending signal from DSP.
31 SL+
32 JP–
I Input tracking jump signal from DSP.
33 JP+
34 TGL I Input tracking gain control signal from DSP. TGL = "H" : Gain low.
35 TOFF I Input tracking off control signal from DSP. TOFF = "H" : Off.
36 TES O Output TES signal to DSP.
37 HFL O HIGH FREQUENCY LEVEL: Detects whether main-beam is on pit or mirror position.
38 SLOF I Input sled servo off control.
39 CV–
I Input CLV error signal from DSP.
40 CV+
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Description
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Pin No. Pin Name I/O
41 RFSM O Output RF.
42 RFS– O Establish RF gain and 3T compensation value from EFM signal with RFSM pin.
43 SLC O SLICE LEVEL CONTROL: Control data slice level by DSP with RF waveform.
44 SLI I Control data slice level by DSP.
45 DGND – Digital GND.
46 FSC O Connected to focus search smoothing capacitor.
47 TBC I TRACKING BALANCE CONTROL: Establish EF balance variable range.
48 NC – Not used.
49 DEF O Output disc defect detection.
50 CLK I Input reference clock. Inputs 4.23MHz from DSP.
51 CL I Input microcomputer command clock.
52 DAT I Input microcomputer command data.
53 CE I Input microcomputer command chip enable.
54 DRF O Detect RF: Output RF level detection.
FOCUS SEARCH SELECT: Switches focus search mode (between ± search
55 FSS I
and + search against reference voltage). (Not used)
56 VCC2 – Servo/digital VCC.
57 REF1 – Connected to reference voltage bypass condenser.
58 VR O Output reference voltage.
59 LF2 – Establish value in detecting disc defect.
60 PHI – Connected to capacitor used to hold peak of RF signal.
61 BHI – Connected to capacitor used to hold bottom of RF signal.
62 LDD O APC-circuit output pin.
63 LDS I APC-circuit input pin.
64 VCC1 – RF VCC.
Description
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