Table of Contents
Advertisement
System Bus
The system bus is the CPU's major connection to all the system
devices, primarily the PCI and EISA bridges, and the memory
controllers. It can handle as many as eight outstanding transactions
at a time through the transaction pipelining feature in which
consecutive tasks from the CPU are queued in and transported to the
designated devices on a first-in first-out basis. Pipelining allows for
transaction overlapping in different phases as the CPU does not have
to wait for each transaction to complete before it issues the next
transaction. This produces significant improvement on overall system
performance.
The bus architecture supports a number of features that ensure high
reliability. It has an 8-bit error correction code (ECC) that protects the
data lines and a 2-bit parity code that protects the address lines.
The bus uses the gunning transceiver logic (GTL+), a synchronous
latched bus protocol that simplifies timing constraints. This protocol
supports higher frequency system designs but requires a low voltage
that reduces electromagnetic interference (EMI) resulting to a lower
power consumption.
PCI and EISA Buses
The system supports two PCI buses created by the two PCI bridge
chipsets (OPB). The PCI buses serve as the links between the PCI
bridges and the PCI devices onboard.
The EISA bus connects the EISA devices to the other system devices
through the PCI/EISA bridge (PCEB) and the EISA system
controller (ESC).
The use of the PCEB and ESC maintains
compatibility with the EISA environment.
1-4
System Guide
Advertisement
Table of Contents
