Sony Betacam BKP-590 Installation And Maintenance Manual page 51

TC7W04F(TOSHIBA)CHIP PACKAGE
TC7W04F-TE12L
C-MOS HEX INVERTERS
(SCALE 3/1)
—TOP VIEW—
1 8 V
DD(+2 to +6V)
1 7
A
2 7
3 5
3
6
GND 4 5 6 2
TL062CPW(TI)FLAT PACKAGE
TL062CPW-E05
OPERATIONAL AMPLIFIER
(J FET INPUT)
—TOP VIEW—
V
DD
1 8
(+1.5 to +18V)
+
–
2 7
+ –
3
6
V
4 EE 5
(–18 to –1.5V)
TLC272CPW(TI)
TLC272CPW-E05
OPERATIONAL AMPLIFIER
—TOP VIEW—
V
DD
1 14
(+3V to +16V)
+
–
2 13
+
–
3 12
4 11
GND
TLC274CPW(TI)FLAT PACKAGE
TLC274CPW-E05
C-MOS OPERATIONAL AMPLIFIER
—TOP VIEW—
1 14
2 13
+ +
– –
3 12
V
DD
GND 11
4
(+3V to +16V)
5 10
– +
6 9
7 8
BKP-590
Y = A Y
Y = A
A Y
0 1
1 0
0 ; LOW LEVEL
1 ; HIGH LEVEL
TMS27C010A-10JL(TI)
C-MOS 1M(131072×8)-BIT EPROM
-TOP VIEW-
V
DD
1 V 32
PP
(+ 5V )
A16 2 31 PGM
IN IN
A15 3 NC 30
IN
A12 4 29 A14
IN IN
A7 5 28 A13
IN IN
A6 6 27 A8
IN IN
A5 7 26 A9
IN IN
A4 8 25 A11
IN IN
A3 9 24 OE
IN IN
A2 10 23 A10
IN IN
A1 11 22 CE
IN IN
A0 12 21 D7
IN IN/OUT
D0 13 20 D6
IN/OUT IN/OUT
D1 14 19 D5
IN/OUT IN/OUT
D2 15 18 D4
IN/OUT IN/OUT
16 GND 17 D3
IN/OUT
READ MODE ( V = + 5V,V = + 5V )
DD PP
OE CE PGM A0-A16 D0-D7 FUNCTION
0 0 1 A IN D OUT ACTIVE
X 1 X X HI-Z STANDBY
1 0 X A IN OUTPUT
HI-Z
X 0 0 A IN
DISABLE
PROGRAM MODE ( V = + 6V,V = + 12.5V )
DD PP
MODE OE CE PGM A0-A16
1 0 0 A IN
1-BYTE
0 0 1 A IN D OUT
PROGRAM
1 0 1 A IN
MODE
1 1 1 A IN
4-BYTE A0,A1 ; X
0 1 0
PROGRAM A2-A16 ; A IN
MODE 0 0 1 A IN D OUT
0 1 1 A IN
2
A16
3
A15
29
A14
28
A13
4
A12 ROW
25
A11 DECODER
23
A10
26
A9
27
A8
5
A7
6
A6
7
A5
8
A4
COLUMN
9
A3
DECODER
10
A2
11
A1
12
A0
24
OE
OE,CE
22
CE
CIRCUIT
31
PGM
DATA INPUT BUFF.
/PROGRAM
CONTROL
12 13
A0 D0
11 14
A1 D1
10 15
A2 D2
9 17
A3 D3
8 18
A4 D4
7 19
A5 D5
6 20
A6 D6
5 21
A7 D7
27
A8
26
A9
23
A10
25
A11
4
A12
28
A13
29
A14
3
A15
2
A16
31
PGM
CE OE
22 24
A0-A16 ; ADDRESS INPUTS
D0-D7 ; DATA INPUTS/OUTPUTS
CE ; CHIP ENABLE INPUT
OE ; OUTPUT ENABLE INPUT
PGM ; PROGRAM INPUT/OUTPUT
ENABLE INPUT
0 ; LOW LEVEL
1 ; HIGH LEVEL
X ; DON'T CARE
HI-Z ; HIGH-IMPEDANCE
D0-D7 FUNCTION
D IN PROGRAM
VERIFY
HI-Z PROGRAM INHIBIT
D IN PROGRAM DATA INPUT
HI-Z PROGRAM
VERIFY
HI-Z PROGRAM INHIBIT
MEMORY
CELL
MATRIX
1024×128×8
COLUMN GATE
OUTPUT
BUFFER
13-15,17-21
D0-D7
4-9
IC