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Asus Aaeon VPC-3350S User Manual

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VPC-3350S
Mobile NVR
User's Manual 1
st
Ed
Last Updated: September 25, 2019

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   Summary of Contents for Asus Aaeon VPC-3350S

  • Page 1 VPC-3350S Mobile NVR User’s Manual 1 Last Updated: September 25, 2019...
  • Page 2 Copyright Notice This document is copyrighted, 2019. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp.  Intel, Pentium, Celeron, and Xeon are registered trademarks of Intel Corporation  Core, Atom are trademarks of Intel Corporation ...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity VPC-3350S If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. All cables and adapters supplied by AAEON are certified and in accordance with the material safety laws and regulations of the country of sale.
  • Page 7 As most electronic components are sensitive to static electrical charge, be sure to ground yourself to prevent static charge when installing the internal components. Use a grounding wrist strap and contain all electronic components in any static-shielded containers. If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii.
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation. Caution: There is a danger of explosion if the battery is incorrectly replaced.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON System QO4-381 Rev.A0 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 × ○ ○ ○ ○ ○ 及其电子组件 外部信号 × ○ ○ ○ ○ ○ 连接器及线材 ○ ○...
  • Page 10 China RoHS Requirement (EN) Hazardous and Toxic Materials List AAEON System QO4-381 Rev.A0 Hazardous or Toxic Materials or Elements Component Name PCB and Components Wires & Connectors for Ext.Connections Chassis CPU & RAM HDD Drive LCD Module Optical Drive Touch Control Module Battery This form is prepared in compliance with the provisions of SJ/T 11364.
  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications ....................1 Specifications ........................ 2 Chapter 2 – Hardware Information .....................5 Dimensions ........................6 2.1.1 Industrial System ..................6 2.1.2 In-Vehicle System ..................9 2.1.3 Main Board ....................11 Jumpers and Connectors ..................12 List of Jumpers ......................
  • Page 12 2.6.3.1 DC-Input (CN1) ................23 2.6.3.2 12VSB Output (CN3) ..............23 2.6.3.3 Board to Board Cable Connector (CN9) ......24 2.6.4 PER-T529 I/O Board Jumpers and Connectors ......25 2.6.5 PER-T529 List of Jumpers ..............25 2.6.5.1 CAN Bus MCU Debug (CN6) ..........26 2.6.5.2 CAN Bus MCU Debug (CN7) ..........
  • Page 13 3.5.2 Chipset: SCC Configuration ..............50 Setup submenu: Security ..................51 3.6.1 Security: Secure Boot ................52 3.6.1.1 Key Management..............53 Setup submenu: Boot ..................... 55 Setup submenu: Save & Exit ................. 56 Chapter 4 – Driver and Software Installation ................. 57 Drivers Download and Installation ..............
  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...
  • Page 15: Specifications

    Specifications System Form Factor Mobile NVR Processor Intel® Apollo Lake Processor Intel® Atom® x5 E3940 (Default) Intel® Pentium® N4200 (Per Project Basis) Intel® Celeron® N3350 (Per Project Basis) Intel® Atom® x7 E3950 (w/ Custom Chassis) Chipset — Main Memory Up to 8GB, DDR3L 204-pin SODIMM Display HDMI x 1 DP x 1...
  • Page 16 System Front I/O Panel CanBus connector x 1 (in-vehicle config, optional) RS-232 x 3 (in-vehicle config., optional) Rear I/O Panel DC-In power x 1 8-bit DIO x 1, 4-ch digital input (Wet/dry contact with Isolation Protection 3,000 VDC), 4-ch digital output (Compatible 5 V/TTL, 31 mA max.
  • Page 17 Power Requirement Power Supply DC 12-24V DC 9-36V with power ignition (in-vehicle config., optional) Mechanical Removable HDD Tray — Internal System HDD Bay — Dimension 160mm (L) x 134mm (W) x 62mm (H) Gross Weight 1.8 kg Note — Note: VPC-3350S is available in two configurations: mobile NVR and in-vehicle NVR. In-vehicle NVR shares the same specifications as mobile NVR with additional I/O ports and different power supply.
  • Page 18: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...
  • Page 19: Dimensions

    Dimensions The VPC-3350S is available in two configurations, Industrial and In-vehicle. You may refer to this section for either configuration. If you have questions about your VPC-3350S or its configuration, please contact your AAEON sales representative. 2.1.1 Industrial System Chapter 2 – Hardware Information...
  • Page 20 Chapter 2 – Hardware Information...
  • Page 21 Chapter 2 – Hardware Information...
  • Page 22: In-vehicle System

    2.1.2 In-Vehicle System Chapter 2 – Hardware Information...
  • Page 23 Chapter 2 – Hardware Information...
  • Page 24: Main Board

    2.1.3 Main Board Chapter 2 – Hardware Information...
  • Page 25: Jumpers And Connectors

    Jumpers and Connectors Top Side Chapter 2 – Hardware Information...
  • Page 26 Bottom Side Chapter 2 – Hardware Information...
  • Page 27: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the system’s jumpers that you can configure for your application. Label Function CN13 Clear CMOS 2.3.1 Clear CMOS (CN13) CN13 Clear CMOS uses a 6-pin configuration. Use two jumpers to connect the pins according to the chart.
  • Page 28: List Of Connectors

    List of Connectors Please refer to the table below for all of the system’s connectors that you can configure for your application Label Function AUDIO1 Front out/Microphone Dual USB3.0 Ethernet 1 without Poe HDMI Connector Front Plane For Option IO Board Connector For Vehicle Application Full Function Mini Card with CN23 CN10...
  • Page 29: Dc Input 12~24v (cn24)

    Label Function LED1 SATA R/W LED Power Button Software Reset 2.4.1 DC Input 12~24V (CN24) Signal Signal 2.4.2 SATA Power Connector (CN14) Signal Signal Chapter 2 – Hardware Information...
  • Page 30: Serial Port 1.2 With Rs232/422/485 (com1)

    2.4.3 Serial Port 1.2 with RS232/422/485 (COM1) Signal Signal DCD(485-/422TX-) RXD(485+/422TX+) TXD(422RX+) DTR(422RX-) 2.4.4 Front Plane (CN4) Signal Signal PWR_SW#(For Car PC) FPANSWH#(For Car PC) HW_RST# FPANSWH# Chapter 2 – Hardware Information...
  • Page 31: Digital Io Connector (cn19)

    2.4.5 Digital IO Connector (CN19) Signal Signal GPIO Port1 GPIO Port5 GPIO Port2 GPIO Port6 GPIO Port3 GPIO Port7 GPIO Port4 GPIO Port8 GPIO Mapping for DIO Connector (CN19) Signal GPIO Mapping Signal GPIO Mapping Bit0 Mapping SIO GP80 Bit4 Mapping SIO GP84 Bit1 Mapping SIO GP81...
  • Page 32: Option Board Dimensions

    Option Board Dimensions The VPC-3350S In-Vehicle configuration comes with two option boards, PER-T528 Power Board, and PER-T529 I/O Board. If you have any questions about the configuration of your VPC-3350S, please contact your AAEON sales representative for assistance. 2.5.1 PER-T528 Power Board Dimensions Chapter 2 –...
  • Page 33: Per-t529 I/o Board Dimensions

    2.5.2 PER-T529 I/O Board Dimensions Chapter 2 – Hardware Information...
  • Page 34: Option Board Assembly

    2.5.3 Option Board Assembly Chapter 2 – Hardware Information...
  • Page 35: Option Board Jumpers And Connectors

    Option Board Jumpers and Connectors The VPC-3350S In-Vehicle configuration comes with two option boards, PER-T528 Power Board, and PER-T529 I/O Board. If you have any questions about the configuration of your VPC-3350S, please contact your AAEON sales representative for assistance. 2.6.1 PER-T528 Power Board Jumpers and Connectors 2.6.2...
  • Page 36: Per-t528 List Of Connectors

    2.6.3 PER-T528 List of Connectors Label Function DC-Input Fuse Slot 12VSB Output MCU Program Header Board To Board Cable Connector 2.6.3.1 DC-Input (CN1) Signal Signal 2.6.3.2 12VSB Output (CN3) Signal Signal +12V +12V Chapter 2 – Hardware Information...
  • Page 37: Board To Board Cable Connector (cn9)

    2.6.3.3 Board to Board Cable Connector (CN9) Signal Signal UART RX Remote_SW# PS_ON# Ignition_SW UART TX Power Button# None Chapter 2 – Hardware Information...
  • Page 38: Per-t529 I/o Board Jumpers And Connectors

    2.6.4 PER-T529 I/O Board Jumpers and Connectors Bottom 2.6.5 PER-T529 List of Jumpers Label Function CAN Bus MCU Debug CAN Bus MCU Debug Chapter 2 – Hardware Information...
  • Page 39: Can Bus Mcu Debug (cn6)

    2.6.5.1 CAN Bus MCU Debug (CN6) Pin Selection Function Normal (Default) Debug 2.6.5.2 CAN Bus MCU Debug (CN7) Pin Selection Function Debug Normal (Default) Chapter 2 – Hardware Information...
  • Page 40: Per-t529 List Of Connectors

    2.6.6 PER-T529 List of Connectors Label Function Com Port (RS232 only) Com Port (RS232 only) Com Port (RS232 only) CAN Bus Connector GPS Antenna Connector Board to Board Connector Full Function mPCIE CN10 Full Function mPCIE 2.6.6.1 CAN Bus Connector (CN4) Signal Signal CAN DATA+...
  • Page 41: Hdd/ssd 2.5" Drive Installation

    HDD/SSD 2.5” Drive Installation This section details the steps to install or remove the 2.5” hard drive or solid state drive (SSD). Before beginning these steps, please ensure the VPC-3350S system is shut down (not in sleep or suspended mode) and the power supply is disconnected. Step 1 Remove the wall mount brackets.
  • Page 42 Step 2 Remove the screws securing the bottom cover. First the side screws, then the COM port fasteners. Chapter 2 – Hardware Information...
  • Page 43 Step 3 Remove the bottom cover by sliding the cover toward the rear. Step 4 Remove the HDD/SSD assembly by removing the screws located on the bottom of the cover. You can now remove the old drive and/or install a new one. Chapter 2 –...
  • Page 44: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...
  • Page 45: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the system will output a few short beeps or display an error message. The system can usually continue the boot up sequence with non-fatal errors.
  • Page 46: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, power on the system and immediately press <Del>...
  • Page 47: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...
  • Page 48: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...
  • Page 49: Advanced: Trusted Computing

    3.4.1 Advanced: Trusted Computing Options Summary Security Device Disabled Support Enabled Optimal Default, Failsafe Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disabled Enabled Optimal Default, Failsafe...
  • Page 50 Options Summary Platform Hierarchy Disabled Enabled Optimal Default, Failsafe Enable or Disable Platform Hierarchy Storage Hierarchy Disabled Enabled Optimal Default, Failsafe Enable or Disable Storage Hierarchy Endorsement Disabled Hierarchy Enabled Optimal Default, Failsafe Enable or Disable Endorsement Hierarchy TPM2.0 UEFI Spec TCG_1_2 Version TCG_2...
  • Page 51: Advanced: Cpu Configuration

    3.4.2 Advanced: CPU Configuration Options Summary Active Processor Cores All Optimal Default, Failsafe Number of cores to enable in each processor package. Hyper-Threading Disabled Enabled Optimal Default, Failsafe Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for Hyper-Threading Technology).
  • Page 52: Advanced: Sata Drives

    3.4.3 Advanced: SATA Drives Options Summary Chipset SATA Disabled Enabled Optimal Default, Failsafe Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports the 2 black internal SATA ports (up to 3Gb/s supported per port). Chapter 3 – AMI BIOS Setup...
  • Page 53: Advanced: Usb Configuration

    3.4.4 Advanced: USB Configuration Options Summary Legacy USB Support Disabled Enabled Optimal Default, Failsafe Enables Legacy USB support. AUTO option disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications. Chapter 3 –...
  • Page 54: Advanced: Sdio Configuration

    3.4.5 Advanced: SDIO Configuration Options Summary Mass Storage Devices: Auto Optimal Default, Failsafe Floppy Forced FDD Hard Disk Mass storage device emulation type. 'AUTO' enumerates devices less than 530MB as floppies. Forced FDD option can be used to force HDD formatted drive to boot as FDD.
  • Page 55: Advanced: Hardware Monitor

    3.4.6 Advanced: Hardware Monitor Chapter 3 – AMI BIOS Setup...
  • Page 56: Advanced: Sio Configuration

    3.4.7 Advanced: SIO Configuration Chapter 3 – AMI BIOS Setup...
  • Page 57: Serial Port 1 Configuration

    3.4.7.1 Serial Port 1 Configuration Options Summary Use This Device Disabled Enabled Optimal Default, Failsafe Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.
  • Page 58: Serial Port 2 Configuration

    3.4.7.2 Serial Port 2 Configuration Options Summary Use This Device Disabled Enabled Optimal Default, Failsafe Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.
  • Page 59: Advanced: Power Management

    3.4.8 Advanced: Power Management Options Summary Power Mode ATX Type Optimal Default, Failsafe AT Type Select Power Supply Mode. Restore AC Power Loss Power Off Power On Last State Optimal Default, Failsafe Select AC power state when power is re-applied after a power failure. RTC wake system from Disabled Optimal Default, Failsafe...
  • Page 60: Advanced: Digital Io Port Configuration

    3.4.9 Advanced: Digital IO Port Configuration Options Summary DIO Port5~8 Output Optimal Default, Failsafe Input Set DIO as Input or Output. Output Level High Optimal Default, Failsafe Set output level when DIO pin is output. Chapter 3 – AMI BIOS Setup...
  • Page 61: Setup Submenu: Chipset

    Setup submenu: Chipset Chapter 3 – AMI BIOS Setup...
  • Page 62: Chipset: North Bridge

    3.5.1 Chipset: North Bridge Options Summary Primary Display Optimal Default, Failsafe PCIE Select which of IGD/PCI Graphics device should be Primary Display Chapter 3 – AMI BIOS Setup...
  • Page 63: Chipset: Scc Configuration

    3.5.2 Chipset: SCC Configuration Options Summary SCC eMMC Support Disabled (D28:F0) Enabled Optimal Default, Failsafe Enable/Disable SCC eMMC Support eMMC Max Speed HS400 Optimal Default, Failsafe HS200 DDR50 Select the eMMC max Speed allowed. Chapter 3 – AMI BIOS Setup...
  • Page 64: Setup Submenu: Security

    Setup submenu: Security Change User/Administrator Password You can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.
  • Page 65: Security: Secure Boot

    3.6.1 Security: Secure Boot Options Summary Secure Boot Disabled Optimal Default, Failsafe Enabled Secure Boot activated when Secure Boot is enabled, Platform Key(PK) is enrolled, System mode is User/Deployed, and CSM is disabled Secure Boot Custom Optimal Default, Failsafe Customization Standard Customizable Secure Boot mode: In Custom mode Secure Boot Policy variables can be configured by a physically...
  • Page 66: Key Management

    3.6.1.1 Key Management Options Summary Factory Key Provision Disabled Optimal Default, Failsafe Enabled Provision factory default keys on next re-boot only when System in Setup Mode Restore Factory Keys Optimal Default, Failsafe Force System to User Mode. Configure NVRAM to contain OEM-defined factory default Secure Boot keys Reset To Setup Mode Optimal Default, Failsafe Delete NVRAM content of all UEFI Secure Boot key databases...
  • Page 67 Options Summary Enroll Efi Image Optimal Default, Failsafe Copy NVRAM content of Secure Boot variables to files in a root folder on a file system device Remove 'UEFI CA' from Optimal Default, Failsafe Device Guard ready system must not list 'Microsoft UEFI CA' Certificate in Authorized Signature database (db) Restore DB defaults Optimal Default, Failsafe...
  • Page 68: Setup Submenu: Boot

    Setup submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Enables or disables Quiet Boot option. CSM Support Disabled Enabled Optimal Default, Failsafe Enable/Disable CSM Support Launch PXE ROM Disabled Optimal Default, Failsafe Enabled Controls the execution of UEFI and Legacy PXE OpROM Network Stack Disabled Optimal Default, Failsafe...
  • Page 69: Setup Submenu: Save & Exit

    Setup submenu: Save & Exit Chapter 3 – AMI BIOS Setup...
  • Page 70: Chapter 4 - Driver And Software Installation

    Chapter 4 Chapter 4 – Driver and Software Installation...
  • Page 71: Drivers Download And Installation

    Drivers Download and Installation Drivers for the VPC-3350S can be downloaded from the product page on the AAEON website. Download the driver(s) you need and follow the steps below to install them. Step 1 – Install Chipset Driver Open the Step1 - Chipset folder followed by SetupChipset.exe Follow the instructions Drivers will be installed automatically Step 2 –...
  • Page 72 Step 5 – Install LAN Driver Open the Step5 - LAN folder and select your OS Open the Setup.exe file in the folder Follow the instructions Drivers will be installed automatically Step 6 – Install Serial Port Driver (optional) Open the Step6 – Serial Port Driver folder followed by Setup.exe file in the folder Follow the instructions Drivers will be installed automatically...
  • Page 73: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...
  • Page 74: Watchdog Timer Initial Program

    Watchdog Timer Initial Program Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Watchdog relative register table Register BitNum Value...
  • Page 75 ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4 #define byte TimerVal // This parameter is represented from Note24...
  • Page 76 ************************************************************************************ VOID Main(){ // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 77 ************************************************************************************ // Procedure : AaeonWDTEnable VOID AaeonWDTEnable (){ WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 1); // Procedure : AaeonWDTConfig VOID AaeonWDTConfig (){ // Disable WDT counting WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 0); // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting(); VOID WDTEnableDisable(byte LDN, byte Register, byte BitNum, byte Value){ SIOBitSet(LDN, Register, BitNum, Value);...
  • Page 78 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...
  • Page 79: Appendix B - Digital I/o Ports

    Appendix B Appendix B – Digital I/O Ports...
  • Page 80: Electrical Specifications For Digital I/o Ports

    Electrical Specifications for Digital I/O Ports GPIO80 ISOGPI0 Input Only GPIO81 ISOGPI1 Input Only GPIO82 ISOGPI2 Input Only GPIO83 ISOGPI3 Input Only GPIO84 ISOGPO0 Output Only GPIO85 ISOGPO1 Output Only GPIO86 ISOGPO2 Output Only GPIO87 ISOGPO3 Output Only Appendix B – Digital I/O Ports...
  • Page 81: Dio Programming

    DIO Programming The VPC-3350S utilizes FINTEK F81866D chipset as its Digital I/O controller. Below are the procedures to complete its configuration. AAEON initial DI/O program is also attached for developing customized program for your application. There are three steps to complete the configuration setup: (1) Enter the MB PnP Mode (2) Modify the data of configuration registers (3) Exit the MB PnP Mode.
  • Page 82: Digital I/o Register

    Digital I/O Register Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Digital Input relative register table Register BitNum Value...
  • Page 83: Digital I/o Sample Program

    Digital I/O Sample Program ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Digital Input Status relative definition (Please reference to Table 2) #define byte DInput1LDN // This parameter is represented from Note3 #define byte DInput1Reg // This parameter is represented from Note4...
  • Page 84 ************************************************************************************ // Digital Output control relative definition (Please reference to Table 3) #define byte DOutput1LDN // This parameter is represented from Note27 #define byte DOutput1Reg // This parameter is represented from Note28 #define byte DOutput1Bit // This parameter is represented from Note29 #define byte DOutput1Val // This parameter is represented from Note30 #define byte DOutput2LDN // This parameter is represented from Note31 #define byte DOutput2Reg // This parameter is represented from Note32...
  • Page 85 ************************************************************************************ VOID Main(){ Boolean PinStatus ; // Procedure : AaeonReadPinStatus // Input : Example, Read Digital I/O Pin 3 status // Output : InputStatus : 0: Digital I/O Pin level is low 1: Digital I/O Pin level is High PinStatus = AaeonReadPinStatus(DInput3LDN, DInput3Reg, DInput3Bit); // Procedure : AaeonSetOutputLevel // Input : Example, Set Digital I/O Pin 6 level...
  • Page 86 ************************************************************************************ Boolean AaeonReadPinStatus(byte LDN, byte Register, byte BitNum){ Boolean PinStatus ; PinStatus = SIOBitRead(LDN, Register, BitNum); Return PinStatus ; VOID AaeonSetOutputLevel(byte LDN, byte Register, byte BitNum, byte Value){ ConfigToOutputMode(LDN, Register, BitNum); SIOBitSet(LDN, Register, BitNum, Value); ************************************************************************************ Appendix B – Digital I/O Ports...
  • Page 87 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...
  • Page 88 ************************************************************************************ Boolean SIOBitRead(byte LDN, byte Register, byte BitNum){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= (1 << BitNum); SIOExitMBPnPMode(); If(TmpValue == 0) Return 0; Return 1; VOID ConfigToOutputMode(byte LDN, byte Register, byte BitNum){ Byte TmpValue, OutputEnableReg; OutputEnableReg = Register-1;...

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