58
DH14
59
DH1
60
DH15
61
DH0
62
SRAMS#
63
SRAMR#
64
A4
65
A5
66
A6
67
A7
68
VDD18
69
A8
70
A13
71
A14
72
A15
73
NC
74
NC
75
GND
76
NC
77
NC
78
NC
79
NC
80
NC
81
NC
82
NC
83
VDD33
84
NC
85
TE#
86
NC
87
HS#
88
NC
89
GND
90
AA#
91
NC
92
NC
93
OP1
94
OP2
95
SCLK
96
SDAT
97
VDD33
98
SUSPEND
99
RPUENO
100
DM
101
DP
102
RS#
103
RMWK#
104
VDD18
105
CKSOCI
106
CKSOCO
107
GND
108
NC
109
NC
110
NC
111
NC
112
NC
113
NC
114
VDD33
115
NC
116
NC
117
VDD18
118
TEST
2003/6 From 3JTech
I/O
High speed data bus bit 14
I/O
High speed data bus bit 1
I/O
High speed data bus bit 15
I/O
High speed data bus bit 0
O
Chip select signal for SRAM
O
Output enable signal for SRAM
O
Address bus bit 4
O
Address bus bit 5
O
Address bus bit 6
O
Address bus bit 7
Power
1.8V power
O
Address bus bit 8
O
Address bus bit 13
O
Address bus bit 14
O
Address bus bit 15
O
Reserved
I
Reserved
Power
Digital ground
O
Reserved
I
Reserved
I
Reserved
O
Reserved
O
Reserved
O
Reserved
I
Reserved
Power
3.3V power
O
Reserved
Control the optional relay to switch off the attached
O
telephone set
O
Reserved
Indicate modem in a V.90 connection or, when flashing,
O
in handshaking procedure
I
Reserved
Power
Digital ground
Indicate modem in auto answer mode or, when flashing,
O
detects an incoming ring signal
I
Reserved
I
Reserved
O
General purpose output pin
O
General purpose output pin
O
Serial clock output for EEPROM
IO
Serial bi-directional data signal for EEPROM
Power
3.3V power
O
USB suspend signal output
O
USB connect or disconnect control
I/O
USB data signal DM(D-)
I/O
USB data signal DP(D+)
I
Reset signal input (active low)
I
Reserved
Power
1.8V power
Crystal oscillator input
I, 1.8V
Crystal oscillator output
O, 1.8V
Power
Digital ground
I
Reserved
I
Reserved
O
Reserved
I
Reserved
I
Reserved
I/O
Reserved
Power
3.3V power
I/O
Reserved
O
Reserved
Power
1.8V power
I, Pull low
Reserved
Revision 1.0
Research & Development
Page 7 of
7
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