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Spectrum Monaco Quad 'C6x VME64 Technical Reference Manual

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Monaco
Quad 'C6x VME64 Board
Technical Reference
Document Number 500-00191
Revision 2.00
September 1999

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Summary of Contents for Spectrum Monaco Quad 'C6x VME64

  • Page 1 Monaco Quad 'C6x VME64 Board Technical Reference Document Number 500-00191 Revision 2.00 September 1999...
  • Page 2 Copyright © 1999 Spectrum Signal Processing Inc. All rights reserved, including those to reproduce this document or parts thereof in any form without permission in writing from Spectrum Signal Processing Inc. All trademarks are registered trademarks of their respective owners. Spectrum Signal Processing reserves the right to change any of the information contained herein without notice.
  • Page 3 Spectrum Signal Processing Preface About Spectrum Signal Processing offers a complete line of DSP hardware, software and I/O Spectrum products for the DSP Systems market based on the latest DSP microprocessors, bus interface standards, I/O standards and software development environments. By delivering quality products, and DSP expertise tailored to specific application requirements, Spectrum can consistently exceed the expectations of our customers.
  • Page 4 Monaco Technical Reference Preface Document Rev. Change 2.00 History Date Changes Sept 1999 Updated for TMS320C6201B and TMS320C6701 DSPs Spectrum Signal Processing Section n.a. Part Number 500-00191 Revision 2.00...

  • Page 5: Table Of Contents

    Spectrum Signal Processing Table of Contents 1 Introduction...1 1.1. Features ...1 1.2. Interfaces ...2 1.2.1. VME...2 1.2.2. PMC ...2 1.2.3. PEM...2 1.2.4. Serial Ports...2 1.2.5. JTAG ...2 1.3. Reference Documents ...3 1.4. General Bus Architecture...4 1.5. On-Board Power Supply ...4 1.6.
  • Page 6 Monaco Technical Reference Table of Contents 3.2.3. Locked Cycles... 21 4 VME64 Bus Interface ... 23 4.1. VME Operation...23 4.2. SCV64 Primary Slave A32/A24 Interface...23 4.3. A24 Secondary Slave Interface...24 4.4. Master A32/A24/A16 SCV64 Interface...27 5 DSP~LINK3 Interface... 29 5.1. DSP~LINK3 Data Transfer Operating Modes ...29 5.2.
  • Page 7 Spectrum Signal Processing DSP~LINK3 Register ...54 ID Register ...55 VME A24 Status Register...56 VME A24 Control Register ...57 10 Specifications ...59 10.1. Board Identification ...59 10.2. General ...60 10.3. Performance and Data Throughput ...61 11 Connector Pinouts ...63 11.1. VME Connectors ...64 11.2.
  • Page 8 Monaco Technical Reference Spectrum Signal Processing Table of Contents viii Part Number 500-00191 Revision 2.00...
  • Page 9 Spectrum Signal Processing List of Figures Figure 1 Block Diagram ...4 Figure 2 Board Layout ...6 Figure 3 Processor Node Block Diagram ...10 Figure 4 DSP Memory Map ...13 Figure 5 DSP Memory Map for External-Memory Space CE1 ...14 Figure 6 Serial Port Routing ...17 Figure 7 Global Bus Arbitration ...20 Figure 8 Primary VME A24/A32 Memory Map ...24 Figure 9 A24 Secondary Interface Memory Map...25...
  • Page 10 Monaco Technical Reference Spectrum Signal Processing Table of Contents Part Number 500-00191 Revision 2.00...
  • Page 11 Spectrum Signal Processing List of Tables Table 1 Reset Summary...5 Table 2 Jumper Settings...7 Table 3 Processor Configurations ...9 Table 4 'C6x Internal Peripheral Register Values...12 Table 5 Processor Boot Source Jumpers...16 Table 6 PEM Connections for Serial Port 0 and 1...18 Table 7 VME and PMC Connections for Serial Port 1...18 Table 8 Global Shared Bus Access...19 Table 9 HPI Register Addresses ...26...
  • Page 12 Monaco Technical Reference Spectrum Signal Processing Table of Contents Part Number 500-00191 Revision 2.00...

  • Page 13: Introduction

    Spectrum Signal Processing 1 Introduction This manual describes the features, architecture, and specifications of the Monaco Quad 'C6x VME64 Board. You can use this information to program the board at a driver level, extend the standard hardware functionality, or develop custom configurations. 1.1.

  • Page 14: Interfaces

    Monaco Technical Reference Introduction 1.2. Interfaces In addition to the VME bus which provides the primary interface to the host computer, the Monaco board features PMC, PEM, serial port, DSP~LINK3 and JTAG interfaces. 1.2.1. Two VMEbus interfaces are provided on the Monaco board. The primary dataflow interface supports VME64 master and slave modes for fast data transfer through the SCV64 interface chip.

  • Page 15: Reference Documents

    Spectrum Signal Processing 1.3. Reference Documents Monaco Installation Guide from Spectrum Monaco Programming Guide from Spectrum DSP~LINK3 Specification from Spectrum PEM Specification from Spectrum TMS320C6000 Peripherals Reference Guide from Texas Instruments SCV64 User Manual from Tundra Semiconductor Corporation Hurricane Data Sheet from Spectrum Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards: PMC IEEE P1386.1/Draft 2.0 available from IEEE VME64 ANSI/VITA 1-1994 available from ANSI...

  • Page 16: General Bus Architecture

    Monaco Technical Reference Introduction 1.4. General Bus Architecture The following block diagram shows the main components of the Monaco board. Node A 'C6x DSP~LINK3 Interface SBSRAM 128K x 32 Site Address Buffer Data Latches Hurricane Global Shared SRAM 512K x 32 VME P2 Connector Figure 1 Block Diagram 1.5.

  • Page 17: Reset Conditions

    Spectrum Signal Processing 1.6. Reset Conditions The Monaco board responds to three types of reset conditions: VME SYSRESET (VME bus /SYSRESET line) VME A24 Slave Interface Reset (VME A24 Control Register bit D0) JTAG reset (JTAG chain /TRST line) The following table indicates which hardware components are reset by the specific reset condition.

  • Page 18: Board Layout

    Monaco Technical Reference Introduction 1.7. Board Layout The following diagram shows the board layout of the Monaco board. Figure 2 Board Layout JP10 PEM Site Nodes C and D JN10 JN11 PEM Site Nodes A and B JN13 JN12 PMC Site JTAG IN JTAG OUT Connector...

  • Page 19: Jumper Settings

    Spectrum Signal Processing 1.8. Jumper settings Table 2 Jumper Settings Jumper JP1 Pins 1-2 JP1 Pins 3-4 JP1 Pins 5-6 JP1 Pins 7-8 JP1 Pins 9-10 JP1 Pins 11-12 JP1 Pins 13-14 JP10 * Default position Note: The default VME A24 slave interface base address is set to 80 0000h. Part Number 500-00191 Revision 2.00 Description...
  • Page 20 Monaco Technical Reference Spectrum Signal Processing Introduction Part Number 500-00191 Revision 2.00...

  • Page 21: Processor Nodes

    Spectrum Signal Processing 2 Processor Nodes The Monaco board supports one, two or four embedded ‘C6X processor nodes shared across the Global Shared Bus. The three possible processor configurations are described in the following figure. Table 3 Processor Configurations Configuration One Node Two Nodes Four Nodes...

  • Page 22: Figure 3 Processor Node Block Diagram

    Monaco Technical Reference Processor Nodes PEM Site Shared with Node Pair Figure 3 Processor Node Block Diagram JTAG Test Bus ‘C6x Host Port Interface (HPI) Bus Node Local Resources Serial Port 0 ‘C6x Serial Port 1 128K x 32 SBSRAM 4M x 32 SDRAM Local...

  • Page 23: Processor Memory Configuration

    Spectrum Signal Processing 2.1. Processor Memory Configuration Each ‘C6X DSP processor implements a 4 Gigabyte (full 32-bit) address space. This address space is partitioned into internal memory space and external memory space. External memory space is accessed through four memory select lines (CE0, CE1, CE2 and CE3).

  • Page 24: Table 4 'C6X Internal Peripheral Register Values

    Monaco Technical Reference Processor Nodes Table 4 'C6x Internal Peripheral Register Values Register Address Value Global Control Register 0x0000 3078 0x0180 0000 EMIF CE0 Control Register 0xFFFF 3F43 0x0180 0008 EMIF CE1 Control Register 0x30E4 0421 0x0180 0004 EMIF CE2 Control Register 0xFFFF 3F33 0x0180 0010 EMIF CE3 Control Register...

  • Page 25: Figure 4 Dsp Memory Map

    Spectrum Signal Processing ‘C6x Addr 0000 0000 0000 1000 0040 0000 0048 0000 0140 0000 0180 0000 01A0 0000 0200 0000 0300 0000 0400 0000 8000 0000 8001 0000 FFFF FFFF Figure 4 DSP Memory Map Part Number 500-00191 Revision 2.00 Memory Contents Internal-Program RAM Reserved...

  • Page 26: Figure 5 Dsp Memory Map For External-Memory Space Ce1

    Monaco Technical Reference Processor Nodes External Memory Space CE1 is dedicated to accessing registers, global shared RAM and DSP~LINK3 (Node A only). Node A differs from nodes B, C and D since it is the only node with access to the DSP~LINK3. The following figure shows the memory map for this region.

  • Page 27: Synchronous Burst Sram

    Spectrum Signal Processing 2.2. Synchronous Burst SRAM The board provides 128K of 32-bit synchronous burst SRAM (SBSRAM) on each ‘C6x local bus. The Monaco board supports 1 wait state operation. 2.3. Synchronous DRAM The board provides 4M of 32-bit synchronous DRAM on each ‘C6x bus. The Monaco board supports 1 wait state operation.

  • Page 28: Processor Booting

    Monaco Technical Reference Processor Nodes 2.7. Processor Booting The ‘C6x can boot from either the VME bus (via its Host Port Interface (HPI) port) or from an 8-bit EEPROM on an installed PEM module. The jumpers listed in the following table select the booting method for each node.

  • Page 29: Serial Port Routing

    Spectrum Signal Processing 2.8. Serial Port Routing Each ‘C6x has two serial ports. Serial Port 0 of each DSP is routed to the PEM connector associated with the DSP node. Routing for Serial Port 1 on nodes A, B, C and D is determined by jumpers J7 to J10 as shown in the figure and following tables.

  • Page 30: Table 6 Pem Connections For Serial Port 0 And 1

    Monaco Technical Reference Processor Nodes Pin assignments for the serial ports are given in the following tables. Table 6 PEM Connections for Serial Port 0 and 1 Signal CLKS CLKR CLKX *The serial port routing jumper corresponding to the node (J7, J8, J9, or J10) must be OUT for port 1 to be routed to the node’s PEM 2 connector.

  • Page 31: Global Shared Bus

    Spectrum Signal Processing 3 Global Shared Bus The Global Shared Bus provides access between devices on the Monaco board as shown in the following table. Table 8 Global Shared Bus Access Target Internal program & data RAM Local SDRAM Local SBSRAM Global Shared RAM Hurricane Registers PMC Site...

  • Page 32: Single Cycle Bus Access

    Monaco Technical Reference Global Shared Bus Bus ownership is cycled between the two highest priority devices (SCV64 and Hurricane) until neither device requires the bus. Then the DSP Nodes are processed round robin. After one pass through the DSP chain, the cycle loops back to include the SCV64 and Hurricane.

  • Page 33: Locked Cycles

    Spectrum Signal Processing Although this is a non-prioritized scheme, the back-off function of the SCV64 interface resolves collisions between a bus master and the VMEbus if there is contention for the VMEbus. Note: There are no ownership timers for the Hurricane or SCV64. If the Hurricane holds the bus too long the VME bus could timeout.
  • Page 34 Monaco Technical Reference Spectrum Signal Processing Global Shared Bus Part Number 500-00191 Revision 2.00...

  • Page 35: Vme64 Bus Interface

    Spectrum Signal Processing 4 VME64 Bus Interface There are two separate VMEbus slave interfaces on the Monaco board. One is implemented by the SCV64 and provides A32 and A24 VMEbus masters access to the global shared bus. The second slave interface provides direct access to the Test Bus Controller for debugging, and to the Host Port Interfaces (HPIs) of each ‘C6x.

  • Page 36: A24 Secondary Slave Interface

    Monaco Technical Reference VME64 Bus Interface VME Offset Address Figure 8 Primary VME A24/A32 Memory Map Note: The full A24 memory map occupies one-quarter of the available A24 space. This can be reduced to the standard 512K (16M ÷ 32) of the available A24 space by mapping only the lower 512 Kbytes (128k x 32) of the global shared SRAM.

  • Page 37: Figure 9 A24 Secondary Interface Memory Map

    Spectrum Signal Processing VME Offset Address Figure 9 A24 Secondary Interface Memory Map Refer to the JTAG Debugging chapter for information on using the Test Bus Controller for JTAG operation. The VME A24 Status Register and the VME A24 Control Register are described in the Registers chapter. Part Number 500-00191 Revision 2.00 00 0000h...

  • Page 38: Table 9 Hpi Register Addresses

    Monaco Technical Reference VME64 Bus Interface The Host Port Interface (HPI) allows a VME host to access the memory map of any ‘C6X. The board transfers 32-bit VME accesses automatically through the 16-bit Host Port Interface as two 16-bit words. The interface consists of three read/write, 32-bit registers that are accessed through the VME A24 slave interface: HPI Address register (HPIA) HPI Control register (HPIC).

  • Page 39: Master A32/A24/A16 Scv64 Interface

    Spectrum Signal Processing Before a host can transfer data through a node’s HPI, the VME host must set the HWOB bit of the node’s HPIC register to “1”. This only has to be done once after the Monaco board is reset. To access an address within a ‘C6x’s memory space, the VME host loads the address into the HPIA register.
  • Page 40 Monaco Technical Reference Spectrum Signal Processing VME64 Bus Interface Part Number 500-00191 Revision 2.00...

  • Page 41: Dsp~Link3 Interface

    Spectrum Signal Processing 5 DSP~LINK3 Interface The Monaco board provides a DSP~LINK3 interface through a ribbon cable connector. The interface supports up to 4 slave DSP~LINK3 devices. The ribbon cable can be up to 12 inches (30 cm) long. The DSP~LINK3 interface is accessed from node A’s local bus only; it is not accessible from any other node nor from the VME bus.

  • Page 42: Address Strobe Control Mode

    Monaco Technical Reference DSP~LINK3 Interface Table 10 DSP~LINK3 Data Transfer Operating Modes Mode Standard Access Standard Fast Access Address Strobe Control Ready Control Access 5.2. Address Strobe Control Mode The Address Strobe Control mode uses the same node A 64K address space as the Standard Fast Access mode.

  • Page 43: Interface Signals

    Spectrum Signal Processing 5.3. Interface Signals The DSP~LINK3 interface consists of two 16-bit bi-directional buffers for data, a 16-bit address latch, and a control signal buffer. The control signals are terminated via a SCSI terminator. The DSP~LINK3 interface signals are: 32 data I/O lines: D[31..0] 16 address outputs: A[15..0] A15 and A14 are used for slave device (board) selection.
  • Page 44 Monaco Technical Reference Spectrum Signal Processing DSP~LINK3 Interface Part Number 500-00191 Revision 2.00...

  • Page 45: Pci Interface

    Spectrum Signal Processing 6 PCI Interface The Hurricane chip provides the interface between the Global Shared SRAM on the Global Shared Bus and the PMC site which supports a 32 bit, 33 MHz PCI bus. Although the DSPs cannot directly master the PCI bus, the Hurricane’s DMA controller provides flexible data transfer between the Global Shared Bus SRAM and the PMC.

  • Page 46: Table 11 Hurricane Register Set

    Monaco Technical Reference PCI Interface Table 11 Hurricane Register Set Hurricane 'C6x PCI Bus DSP Offset Address Offset 0x00 0x016C 0000 0x0020 0000 0x01 0x016C 0004 0x0020 0004 0x02 0x016C 0008 0x0020 0008 0x03 0x016C 000C 0x0020 000C 0x04 0x016C 0010 0x0020 0010 0x05 0x016C 0014...
  • Page 47 Spectrum Signal Processing Hurricane 'C6x PCI Bus DSP Offset Address Offset 0x28 0x016C 00A0 0x0020 00A0 0x29 0x016C 00A4 0x0020 00A4 0x2A 0x016C 00A8 0x0020 00A8 0x2B 0x016C 00AC 0x0020 00AC 0x2C 0x016C 00B0 0x0020 00B0 0x2D 0x016C 00B4 0x0020 00B4 0x2E 0x016C 00B8 0x0020 00B8 0x2F...

  • Page 48: Hurricane Implementation

    Monaco Technical Reference PCI Interface Hurricane 'C6x PCI Bus DSP Offset Address Offset 0x4F 0x016C 013C 0x0020 013C 0x50 0x016C 0140 0x0020 0140 6.2. Hurricane Implementation The Hurricane PCI-to-DSP Bridge Data Sheet should be read in order to understand how it is used with the Monaco board. On the DSP port of the Hurricane, only bank 0 is used to access the Global Shared Bus.

  • Page 49: Jtag Debugging

    Spectrum Signal Processing 7 JTAG Debugging The Monaco board supports JTAG in-circuit emulation from a built in 74ACT8990 Test Bus Controller. The 74ACT8990 Test Bus Controller permits the VME interface to operate the JTAG chain. There are also two JTAG connectors for an XDS510 or White Mountain debugger, JTAG IN (J1) and JTAG OUT (J2), which can route the JTAG chain off-board.
  • Page 50 Monaco Technical Reference JTAG Debugging For multiple Monaco boards, the JTAG cable of the external debugger should be connected to the JTAG IN of the first board. The JTAG OUT of the first board should be connected to the JTAG IN of second board. The JTAG OUT of the second board should be connected to the JTAG IN of third board and so on.

  • Page 51: Interrupt Handling

    Spectrum Signal Processing 8 Interrupt Handling 8.1. Overview Each ‘C6x has four interrupt pins which are configurable as either leading or falling edge-triggered interrupts. For the Monaco board, all ‘C6x interrupts are configured as rising edge-triggered interrupts. The /NMI interrupts for the ‘C6x DSPs are not used; they are tied high.

  • Page 52: Dsp~Link3 Interrupts To Node A

    Monaco Technical Reference Interrupt Handling SCV64 Interrupt BUSERR_D VINTD BUSERR_C VINTC BUSERR_B VINTB BUSERR_A VINTA Hurricane PCI Bus Interrupts DSP~LINK3 Interface Interrupts Figure 12 Interrupt Routing 8.2. DSP~LINK3 Interrupts to Node A The four active-low interrupts from the DSP~LINK3 interface are logically OR’ed and routed to the INT7 interrupt input of the node A ‘C6x.

  • Page 53: Pem Interrupts

    Spectrum Signal Processing 8.3. PEM Interrupts There are two active-low, driven interrupts from the PEM connectors for each node. These interrupts (/PEM INT1 and /PEM INT2) are OR’ed together. Their output is routed to INT6 of each node’s DSP and inverted to create a rising-edge trigger. The Monaco board does not latch the PEM interrupts.

  • Page 54: Table 12 Kipl Status Bits And The Iack Cycle

    Monaco Technical Reference Interrupt Handling The /KIPL[2..0] status bits, D[2..0], in the VSTATUS Register indicate the priority level of the SCV64 interrupt. These bits reflect the state of the /KIPL lines from the SCV64. If all three active-low bits are set to “1” (inactive), then an SCV64 interrupt did not cause the INT4 interrupt.

  • Page 55: Bus Error Interrupts

    Spectrum Signal Processing SCV64 interrupts can be generated from the VMEbus (vectored) or internally by the SCV64 (auto-vectored). If the interrupt was caused by an external VMEbus interrupt the SCV64 initiates an /IACK cycle on the VMEbus. The /IACK cycle is acknowledged by the interrupter which puts its interrupt vector on the lower 8 data bits of the DSP’s data bus.

  • Page 56: Inter-Processor Interrupts

    Monaco Technical Reference Interrupt Handling 8.8. Inter-processor Interrupts The Inter-processor interrupts (VINTx) are shared with the SCV interrupt. They allow any processor to interrupt any other processor through the VINTx registers. There are four of these registers; one for each of the processors. To generate an interrupt to a particular processor, a “1”...

  • Page 57: Registers

    Spectrum Signal Processing 9 Registers This section provides a reference to the registers that are unique to the Monaco board. Information for the registers within the SCV64 bus interface chip, the ACT8990 Test Bus Controller (TBC), and the Hurricane PCI interface chip can be found in their respective data sheets.

  • Page 58: Vpage Register

    Monaco Technical Reference Registers VPAGE Register Address: 016D 0000h D31.. D23.. KADDR27 Reserved This register sets certain SCV64 address and control lines in order to extend the address range of the ‘C6x processors and set up the type of VME cycle to be performed. Each node has its own register.

  • Page 59: Vstatus Register

    Spectrum Signal Processing VSTATUS Register Address: 016D 8000h D31.. D23.. BUSERRD This register is used by a processor to identify the source of an INT4 interrupt. VINTD VINTC VINTB VINTA BUSERRD BUSERRC BUSERRB Part Number 500-00191 Revision 2.00 Reserved Reserved Reserved BUSERRC BUSERRB...
  • Page 60 Monaco Technical Reference Registers BUSERRA KAVEC /KIPL2..0 on reset. Status of the last bus cycle access made to the SCV64 by node A, including SCV64 register and VME master accesses. Set to “1” if there was an error. Cleared by writing “10h” to the VSTATUS register. All other interrupts are cleared when the source of the interrupt is cleared.

  • Page 61: Vinta Register

    Spectrum Signal Processing VINTA Register Address: 016D 8004h D31.. D7.. This register allows any processor to generate or clear an interrupt to node A. Upon reset this value is ‘0’. To generate an interrupt to node A, set bit D0 of this register to “1”. To clear an interrupt to node A, set bit D0 of this register to “0”.

  • Page 62: Vintb Register

    Monaco Technical Reference Registers VINTB Register Address: 016D 8008h D31.. D7.. This register allows any processor to generate or clear an interrupt to node B. Upon reset this value is ‘0’. To generate an interrupt to node B, set bit D0 of this register to “1”. To clear an interrupt to node B, set bit D0 of this register to “0”.

  • Page 63: Vintc Register

    Spectrum Signal Processing VINTC Register Address: 016D 800Ch D31.. D7.. This register allows any processor to generate or clear an interrupt to node C. Upon reset this value is ‘0’. To generate an interrupt to node C, set bit D0 of this register to “1”. To clear an interrupt to node C, set bit D0 of this register to “0”.

  • Page 64: Vintd Register

    Monaco Technical Reference Registers VINTD Register Address: 016D 8010h D31.. D7.. This register allows any processor to generate or clear an interrupt to node D. Upon reset this value is ‘0’. To generate an interrupt to node D, set bit D0 of this register to “1”. To clear an interrupt to node D, set bit D0 of this register to “0”.

  • Page 65: Kipl Enable Register

    Spectrum Signal Processing KIPL Enable Register Address: 016D 8014h D31.. D7.. The KIPL Enable Register is used to enable interrupts generated from the SCV64 to be sent to a particular processor node. The /KIPL lines represent VME interrupts, location monitor interrupt, SCV64 DMA, and SCV64 timer interrupts. These enable bits do not affect the individual KBERR interrupt bits.

  • Page 66: Dsp~Link3 Register

    Monaco Technical Reference Registers DSP~LINK3 Register Address: 016D 8018h D31.. D7.. Processor node A uses this register assert or release reset to the DSP~LINK3 interface its local bus. It is also used to control the operation of DSP~LINK3 standard fast accesses. DL3_RESET ASTRB_EN This read/write register is not accessible from nodes B, C, or D.

  • Page 67: Id Register

    Spectrum Signal Processing ID Register Address: 016D 801Ch D31.. D7.. This register allows DSP software to identify which processor it is running on. Each of the four bits in the register correspond to a particular processor node. A node can read the status of all four bits but can only write to its own bit.

  • Page 68: Vme A24 Status Register

    Monaco Technical Reference Registers VME A24 Status Register VME A24 Secondary Base Address + 1000h D31.. D7.. The VME host reads this register to determine the state of the HINT lines from each processor node. Each bit corresponds to one of the four processor nodes. The state of the bit is simply a reflection of the HINT bit value in the corresponding ‘C6x HPIC register.

  • Page 69: Vme A24 Control Register

    Spectrum Signal Processing VME A24 Control Register VME A24 Secondary Base Address + 1004h D31.. D7.. The VME host uses this register to reset all Monaco board devices except for the SCV64 bus interface chip. To reset the board, the VME host writes a “0” to bit D0. This read/write register is accessed from the VME A24 bus.
  • Page 70 Monaco Technical Reference Spectrum Signal Processing Registers Part Number 500-00191 Revision 2.00...

  • Page 71: Specifications

    Spectrum Signal Processing 10 Specifications 10.1. Board Identification Power, current, and data throughput specifications depend upon the type and version of processors used on the board. Monaco Monaco67 The processor type and version can be identified by examining the DSPs on the board; earlier DSPs have the marking “C21”, while TMS320C6201B chips are marked “C31”.

  • Page 72: General

    Monaco Technical Reference Specifications 10.2. General Table 14 Specifications Parameter Current Consumption +5 Volts +12 Volts -12 Volts Power Height Width Operating Temperature Monaco Monaco TMS320C6201B TMS320C6201 3.6 Amps 8.8 Amps 0 Amps 0 Amps 0 Amps 0 Amps 18 Watts 44 Watts 1 VME slot 0°...

  • Page 73: Performance And Data Throughput

    Spectrum Signal Processing 10.3. Performance and Data Throughput The following table gives the data transfer rates between different memory, processor and interface resources on the Monaco board. Monaco boards using the TMS320C6201 processor have a clock speed of 200 MHz; Monaco67 boards using the TMS230C6701 processor have a clock speed of 167 MHz.
  • Page 74 Monaco Technical Reference Spectrum Signal Processing Specifications Part Number 500-00191 Revision 2.00...

  • Page 75: Connector Pinouts

    Spectrum Signal Processing 11 Connector Pinouts Figure 13 Connector Layout Part Number 500-00191 Revision 2.00 Node Node 60 59 JN10 JN11 Node JN13 JN12 Node JTAG IN JTAG OUT Connector Connector Monaco Technical Reference Connector Pinouts Node D ‘C6x Node C ‘C6x Node B ‘C6x...

  • Page 76: Vme Connectors

    Monaco Technical Reference Connector Pinouts 11.1. VME Connectors VME connector P1 is a standard 96-pin DIN 3-row connector. VME connector P2 is standard 160-pin DIN 5-row connector. The Monaco board will be factory configured to route either the PMC or DSP~LINK3 connector to P2. Refer to the appropriate pinout for your board for this.

  • Page 77: Table 17 Vme P2 Connector Pinout (Pmc To Vme P2)

    Spectrum Signal Processing Table 17 VME P2 Connector Pinout (PMC to VME P2) Pin # Z Row Signal Part Number 500-00191 Revision 2.00 A Row Signal B Row Signal PMC JN4-2 PMC JN4-4 CLKS_C1 PMC JN4-6 PMC JN4-8 CLKR_C1 PMC JN4-10 PMC JN4-12 CLKX_C1 PMC JN4-14...

  • Page 78: Table 18 Vme P2 Connector (Dsp~Link3 To Vme P2)

    Monaco Technical Reference Connector Pinouts Table 18 VME P2 Connector (DSP~LINK3 to VME P2) Pin # Z Row Signal A Row Signal B Row Signal DL3_A14 CLKS_C1 DL3_A12 DL3_A10 CLKR_C1 DL3_A8 DL3_A6 CLKX_C1 DL3_A4 DL3_A2 DR_C1 DL3_A0 /DL3_RESET DX_C1 /DL3_DSTRB /DL3_ASTRB FSR_C1 /DL3_RDY...

  • Page 79: Pmc Connectors

    Spectrum Signal Processing 11.2. PMC Connectors The PMC Connectors use a standard CMC style 1mm pitch SMT connector. Table 19 PMC Connector JN1 Pinout Pin # Part Number 500-00191 Revision 2.00 Signal Pin # INTB# BMODE1# INTD# REQ# V(I/O) AD28 AD25 AD22 AD19...

  • Page 80: Table 20 Pmc Connector Jn2

    Monaco Technical Reference Connector Pinouts Table 20 PMC Connector JN2 Pin # Signal Pin # +12V RSVD BMODE2# RST# BMODE3# +3.3V BMODE4# RSVD AD30 AD24 IDSEL +3.3V AD18 AD16 TRDY# PERR# +3.3V BE1# AD14 +3.3V RSVD RSVD ACK64# Spectrum Signal Processing Signal TRST# RSVD...

  • Page 81: Table 21 Pmc Connector Jn4

    Spectrum Signal Processing Table 21 PMC Connector JN4 Pin # Part Number 500-00191 Revision 2.00 Signal Pin # Signal P2C1 P2A1 P2C2 P2A2 P2C3 P2A3 P2C4 P2A4 P2C5 P2A5 P2C6 P2A6 P2C7 P2A7 P2C8 P2A8 P2C9 P2A9 P2C10 P2A10 P2C11 P2A11 P2C12 P2A12...

  • Page 82: Table 22 Non-Standard Pmc Connector Jn5

    Monaco Technical Reference Connector Pinouts Table 22 Non-standard PMC Connector JN5 Pin # Signal Pin # CLKS_A1 CLKS_C1 CLKR_A1 CLKR_C1 CLKX_A1 CLKX_C1 DR_A1 DX_A1 FSR_A1 FSR_C1 FSX_A1 FSX_C1 CLKS_B1 CLKS_D1 CLKR_B1 CLKR_D1 CLKX_B1 CLKX_D1 DR_B1 DX_B1 FSR_B1 FSR_D1 FSX_B1 FSX_D1 Reserved Reserved Reserved...

  • Page 83: Pem Connectors

    Spectrum Signal Processing 11.3. PEM Connectors Both PEM connectors use 60 pin 0.8mm pitch SMT connectors. PEM_CON1 is the closest to the front panel. Table 23 PEM 1 Connector Pinout Pin # Part Number 500-00191 Revision 2.00 Signal Pin # 32MHz EA10 EA11...

  • Page 84: Table 24 Pem 2 Connector Pinout

    Monaco Technical Reference Connector Pinouts Table 24 PEM 2 Connector Pinout Pin # Signal Pin # CLKX1 FSX1 FSR1 CLKR1 CLKS1 RSVD /PEM_CE2 RSVD /HOLD /HOLDA RSVD EA20 EA21 RSVD +3.3V +3.3V /BE0 /BE1 /BE2 /BE3 /SDRAS /SDCAS /PEM_INT2 /SDWE PEM_TIMER Spectrum Signal Processing Signal...

  • Page 85: Jtag Connectors

    Spectrum Signal Processing 11.4. JTAG Connectors Both JTAG connectors use 2 x 7, 0.1” x 0.1” bare pin headers. Table 25 JTAG IN Connector Pinout Pin # Table 26 JTAG OUT Connector Pin # Part Number 500-00191 Revision 2.00 Signal Pin # key (no pin) TCK_RET...
  • Page 86 Monaco Technical Reference Spectrum Signal Processing Connector Pinouts Part Number 500-00191 Revision 2.00...

  • Page 87: Table 27 Scv64 Register Initialization

    Spectrum Signal Processing Appendix A: SCV64 Register Values This appendix briefly describes the default register settings for the SCV64 on the Monaco board. The following table shows the default values that are programmed into the registers by the initialization code supplied with the Monaco board. Table 27 SCV64 Register Initialization ‘C6x Address Register 016E 0000h...
  • Page 88 Monaco Technical Reference SCV64 Register Values Table 27 SCV64 Register Initialization ‘C6x Address Register 016E 00A4h 016E 00A8h 016E 00ACh 016E 00B0h 016E 00B4h 016E 00B8h 016E 00BCh 016E 00C0h 016E 00C4h 016E 00C8h 016E 00CCh 016E 00D0h 016E 00D4h 016E 00D8h 016E 00DCh 016E 00E0h...
  • Page 89 Spectrum Signal Processing Index A24 slave interface reset, 5 arbitration global shared bus, 19 Auto-Syscon capability, 27 backplane connectors VME bus, 23 base address, VME A24 slave interface setting via jumpers, 7 block diagram, 4 processor node, 10 board layout diagram, 6 boot mode setting via jumpers, 7 boot source of DSP, setting, 16...
  • Page 90 Monaco Technical Reference Index interrupts to node A, 40 register, 54 reset, 31 assert or release, 54 standard fast accesses, control, 54 EEPROM, 16 enable interrupt from SCV64 to a node, 53 external memory space of DSP, 11 features of the board, 1 fixed-point, 1 floating-point, 1 generate interrupt...
  • Page 91 Spectrum Signal Processing JTAG OUT connector, 73 jumper settings, 7 setting DSP boot source, 16 KIPL enable register, 53 status bits, 42 locked cycle (global shared bus access), locking global shared bus, 21 precautions to follow, 21 memory configuration, DSP, 11 global shared bus, 19 DSP, 13 external-memory space CE1, 14...
  • Page 92 Monaco Technical Reference Index port1 VME and PMC connections, 18 routing, 17 setting via jumpers, 7 single cycle global shared bus access, specifications data throughput, 61 performance, 61 synchronous burst SRAM, 15 synchronous DRAM, 15 SYSRESET, 5 TBC, 37 Test Bus Controller, 37 throughput specifications, 61 TMS320C6201, 1, 9 TMS320C6701, 1, 9...

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