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National Semiconductor ST-NIC DP83902A Manual

Serial network interface controller for twisted pair
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DP83902A
DP83902A ST-NIC(TM) Serial Network Interface Controller for Twisted Pair
Literature Number: SNLS082A

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Summary of Contents for National Semiconductor ST-NIC DP83902A

  • Page 1 DP83902A DP83902A ST-NIC(TM) Serial Network Interface Controller for Twisted Pair Literature Number: SNLS082A...

  • Page 2: System Diagram

    Network statistics storage 1 0 System Diagram Station or DTE TL F 11157 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation ST-NIC is a trademark of National Semiconductor Corporation C 1995 National Semiconductor Corporation TL F 11157...

  • Page 3: Table Of Contents

    General Description Table Of Contents (Continued) The Media Access Control function which is provided by the 1 0 SYSTEM DIAGRAM Network Interface Control module (NIC) provides simple 2 0 PIN DESCRIPTION and efficient packet transmission and reception control by 3 0 BLOCK DIAGRAM means of unique dual DMA channels and an internal FIFO 4 0 FUNCTIONAL DESCRIPTION Bus arbitration and memory control logic are integrated to...
  • Page 4 Connection Diagrams (Continued) TL F 11157 – 56 Order Number DP83902AVLJ See NS Package Number VLJ100A...

  • Page 5: Pin Description

    Connection Diagrams (Continued) TL F 11157 – 65 Order Number DP83902AVJG See NS Package Number VJG100A 2 0 Pin Description PQFP PLCC AVJG Description Pin No Pin No Pin No Name BUS INTERFACE PINS INTERRUPT Indicates that the DP83902A requires CPU attention after reception transmission or completion of DMA transfers The interrupt is cleared by writing to the ISR (Interrupt Status Register) All interrupts are maskable WACK...
  • Page 6 2 0 Pin Description (Continued) PQFP PLCC AVJG Description Pin No Pin No Pin No Name BUS INTERFACE PINS (Continued) 4 –8 12–23 2–4 6 AD0– I O Z MULTIPLEXED ADDRESS DATA BUS 10 –12 28–31 7 9–15 AD15 Register Access with DMA inactive CS low and ACK returned from 14 15 17 20–23 DP83902A pins AD0–AD7 are used to read and write register data AD8–...
  • Page 7 2 0 Pin Description (Continued) PQFP PLCC AVJG Description Pin No Pin No Pin No Name BUS INTERFACE PINS (Continued) BACK BUS ACKNOWLEDGE Bus Acknowledge is an active high signal indicating that the CPU has granted the bus to the DP83902A If immediate bus access is desired BREQ should be tied to BACK Tying BACK to V will result in a deadlock...
  • Page 8 2 0 Pin Description (Continued) PQFP PLCC AVJG Description Pin No Pin No Pin No Name NETWORK INTERFACE PINS (Continued) AUI TPI SELECT A TTL level active high input that selects either the AUI interface or the TPI module for interface with the ENDEC module When high the AUI is selected when low the TPI is selected 76 77 73 74...

  • Page 9: Block Diagram

    3 0 Block Diagram TL F 11157 – 3 FIGURE 1 Typical Connection to Twisted Pair Cable TL F 11157 – 4 Recommended integrated modules are 1) Pulse Engineering PE65431 2) Belfuse 0556-2006-01 or 0556-3392-00 3) Valor FL1012 ST-NIC Twisted Pair Interface...

  • Page 10: Functional Description

    4 0 Functional Description (Refer to Figure 1 ) TWISTED PAIR INTERFACE (TPI) MODULE The reduced squelch mode functions the same as the 10BASE-T mode except that only the lower level is used for The TPI consists of five main logical functions both turn-on and turn-off a) The Smart Squelch responsible for determining when valid data is present on the differential receive inputs...
  • Page 11 4 0 Functional Description (Continued) These four signals are resistively combined TXO with Transmit during idle with SEL high (for IEEE 802 3) TXOd and TXO with TXOd This is known as digital Transmit and Transmit are equal in the idle state This pre-emphasis and is required to compensate for the twisted provides zero differential voltage to operate with transform- pair cable which acts like a low pass filter causing greater...
  • Page 12 4 0 Functional Description (Continued) In order to prevent distortion on the transmitted frequency ADDRESS RECOGNITION LOGIC the total capacitance seen by the crystal should equal the The address recognition logic compares the Destination Ad- total load capacitance On a standard parallel set-up as dress Field (first 6 bytes of the received packet) to the Phys- shown in the diagram below the 2 load caps C1 and C2 ical address registers stored in the Address Register Array...

  • Page 13: Transmit Receive Packet

    4 0 Functional Description (Continued) 3 ST-NIC flushes remaining bytes from FIFO bus timing External arbitration is performed with a standard bus request bus acknowledge handshake protocol 4 ST-NIC performs internal processing to prepare for writ- ing the header 5 0 Transmit Receive Packet 5 ST-NIC writes 4-byte (2-word) header Encapsulation Decapsulation 6 ST-NIC de-asserts BREQ...

  • Page 14: Direct Memory Access Control (Dma

    5 0 Transmit Receive Packet 6 0 Direct Memory Access Encapsulation Decapsulation Control (DMA) (Continued) The DMA capabilities of the ST-NIC greatly simplify the use of the DP83902A in typical configurations The local DMA SOURCE ADDRESS channel transfers data between the FIFO and memory On The source address is the physical address of the node that transmission the packet is DMAed from memory to the sent the packet Source addresses cannot be multicast or...

  • Page 15: Packet Reception

    7 0 Packet Reception The Local DMA receive channel uses a Buffer Ring Struc- ic provides three basic functions linking receive buffers for ture comprised of a series of contiguous fixed length long packets recovery of buffers when a packet is rejected 256-byte (128 word) buffers for storage of received packets and recirculation of buffer pages that have been read by the The location of the Receive Buffer Ring is programmed in...
  • Page 16 7 0 Packet Reception (Continued) INITIALIZATION OF THE BUFFER RING ing a packet and is advanced when a packet is removed A simple analogy to remember the function of these registers Two static registers and two working registers control the is that the Current Page Register acts as a Write Pointer and operation of the Buffer Ring These are the Page Start Reg- the Boundary Pointer acts as a Read Pointer...
  • Page 17 7 0 Packet Reception (Continued) LINKING RECEIVE BUFFER PAGES Receive Buffer Ring value programmed in the Page Start Address Register The second comparison tests for equality If the length of the packet exhausts the first 256-byte buffer between the DMA address of the next buffer address and the DMA performs a forward link to the next buffer to store the contents of the Boundary Pointer Register If the two the remainder of the packet For a maximum length packet...
  • Page 18 7 0 Packet Reception (Continued) Buffer Ring Overflow the ST-NIC once the overflow routine is completed (as in step 11) Also it is possible for the ST-NIC to defer indef- If the Buffer Ring has been filled and the DMA reaches the initely when it is stopped on a busy network Step 5 also Boundary Pointer Address reception of the incoming pack- alleviates this problem Step 5 is essential and should...
  • Page 19 7 0 Packet Reception (Continued) 6 Place the ST-NIC in either mode 1 or mode 2 loopback 10 Take the ST-NIC out of loopback This is done by writ- This can be accomplished by setting bits D2 and D1 of ing the Transmit Configration Register with the value it the Transmit Configuration Register to ‘‘0 1’’...
  • Page 20 7 0 Packet Reception (Continued) Enabling the ST-NIC On An Active Network 10 Put ST-NIC in START mode (Command Register 22H) The local receive DMA is still not active since the After the ST-NIC has been initialized the procedure for dis- ST-NIC is in LOOPBACK abling and then re-enabling the ST-NIC on the network is similar to handling Receive Buffer Ring overflow as de-...
  • Page 21 7 0 Packet Reception (Continued) BUFFER RECOVERY FOR REJECTED PACKETS errors The received CRC is always stored in buffer memory after the last byte of received data for the packet If the packet is a runt packet or contains CRC or Frame Alignment errors it is rejected The buffer management log- Error Recovery ic resets the DMA back to the first buffer page used to store...
  • Page 22 7 0 Packet Reception (Continued) REMOVING PACKETS FROM THE RING AD15 AD8 AD7 Packets are removed from the ring using the Remote DMA Next Packet Pointer Receive Status or an external device When using the Remote DMA the Receive Byte Count 0 Receive Byte Count 1 Send Packet command can be used This programs the Re- mote DMA to automatically remove the received packet...

  • Page 23: Packet Transmission

    8 0 Packet Transmission The Local DMA is also used during transmission of a pack- TRANSMIT PACKET ASSEMBLY FORMAT et Three registers control the DMA transfer during trans- The following diagrams describe the format for how packets mission a Transmit Page Start Address Register (TPSR) must be assembled prior to transmission for different byte and the Transmit Byte Count Registers (TBCR0 1) When ordering schemes The various formats are selected in the...

  • Page 24: Remote Dma

    9 0 Remote DMA The Remote DMA channel is used to both assemble pack- sequentially read data from the local buffer memory begin- ets for transmission and to remove received packets from ning at the Remote Start Address and write data to the I O the Receive Buffer Ring It may also be used as a general port The DMA Address will be incremented and the Byte purpose slave DMA channel for moving blocks of data or...

  • Page 25: Internal Registers

    10 0 Internal Registers All registers are 8-bit wide and mapped into four pages monly accessed during ST-NIC operation while page 1 reg- which are selected in the Command Register (PS0 PS1) isters are used primarily for initialization The registers are Pins RA0–RA3 are used to address registers within each partitioned to avoid having to perform two write read cycles page Page 0 registers are those registers which are com-...
  • Page 26 10 0 Internal Registers (Continued) Page 1 Address Assignments (PS1 0 PS0 Page 2 Address Assignments (PS1 1 PS0 RA0 –RA3 RA0– RA3 Command (CR) Command (CR) Command (CR) Command (CR) Physical Address Physical Address Page Start Register Current Local DMA Register 0 (PAR0) Register 0 (PAR0) (PSTART)
  • Page 27 10 0 Internal Registers (Continued) 10 3 REGISTER DESCRIPTIONS COMMAND REGISTER (CR) 00H (READ WRITE) The Command Register is used to initiate transmissions enable or disable Remote DMA operations and to select register pages To issue a command the microprocessor sets the corresponding bit(s) (RD2 RD1 RD0 TXP) Further commands may be overlapped but with the following rules (1) If a transmit command overlaps with a remote DMA operation bits RD0 RD1 and RD2 must be maintained for the remote DMA command when setting the TXP bit Note if a remote DMA command is re-is- sued when giving the transmit command the DMA will complete immediately if the remote byte count register has not been...
  • Page 28 10 0 Internal Registers (Continued) 10 3 REGISTER DESCRIPTIONS (Continued) INTERRUPT STATUS REGISTER (ISR) 07H (READ WRITE) This register is accessed by the host processor to determine the cause of an interrupt Any interrupt can be masked in the Interrupt Mask Register (IMR) Individual interrupt bits are cleared by writing a ‘‘1’’ into the corresponding bit of the ISR The INT signal is active as long as any unmasked signal is set and will not go low until all unmasked bits in this register have been cleared The ISR must be cleared after power up by writing it with all 1’s Symbol...
  • Page 29 10 0 Internal Registers (Continued) 10 3 REGISTER DESCRIPTIONS (Continued) INTERRUPT MASK REGISTER (IMR) 0FH (WRITE) The Interrupt Mask Register is used to mask interrupts Each interrupt mask bit corresponds to a bit in the Interrupt Status Register (ISR) If an interrupt mask bit is set an interrupt will be issued whenever the corresponding bit in the ISR is set If any bit in the IMR is set low an interrupt will not occur when the bit in the ISR is set The IMR powers up to all zeroes RDCE CNTE OVWE TXEE RXEE...
  • Page 30 10 0 Internal Registers (Continued) 10 3 REGISTER DESCRIPTIONS (Continued) DATA CONFIGURATION REGISTER (DCR) 0EH (WRITE) This Register is used to program the ST-NIC for 8- or 16-bit memory interface select byte ordering in 16-bit applications and establish FIFO thresholds The DCR must be initialized prior to loading the Remote Byte Count Registers LAS is set on power up Symbol Description...
  • Page 31 10 0 Internal Registers (Continued) 10 3 REGISTER DESCRIPTIONS (Continued) TRANSMIT CONFIGURATION REGISTER (TCR) 0DH (WRITE) The transmit configuration establishes the actions of the transmitter section of the ST-NIC during transmission of a packet on the network LB1 and LB0 which select loopback mode power up as 0 OFST ATD Symbol Description...
  • Page 32 10 0 Internal Registers (Continued) 10 3 REGISTER DESCRIPTIONS (Continued) TRANSMIT STATUS REGISTER (TSR) 04H (READ) This register records events that occur on the media during transmission of a packet It is cleared when the next transmission is initiated by the host All bits remain low unless the event that corresponds to a particular bit occurs during transmission Each transmission should be followed by a read of this register The contents of this register are not specified until after the first transmission Symbol...
  • Page 33 10 0 Internal Registers (Continued) 10 3 REGISTER DESCRIPTIONS (Continued) RECEIVE CONFIGURATION REGISTER (RCR) 0CH (WRITE) This register determines operation of the ST-NIC during reception of a packet and is used to program what types of packets to accept Symbol Description Save Errored Packets 0 Packets with receive errors are rejected...
  • Page 34 10 0 Internal Registers (Continued) 10 3 REGISTER DESCRIPTIONS (Continued) RECEIVE STATUS REGISTER (RSR) 0CH (READ) This register records status of the received packet including information on errors and the type of address match either physical or multicast The contents of this register are written to buffer memory by the DMA after reception of a good packet If packets with errors are to be saved the receive status is written to memory at the head of the erroneous packet if an erroneous packet is received If packets with errors are to be rejected the RSR will not be written to memory The contents will be cleared when the next packet arrives CRC errors Frame Alignment errors and missed packets are counted internally by the ST-NIC...
  • Page 35 10 0 Internal Registers (Continued) 10 4 DMA REGISTERS DMA Registers TL F 11157 – 19 The DMA Registers are partitioned into groups Transmit Bit Assignment Receive and Remote DMA Registers The Transmit regis- ters are used to initialize the Local DMA Channel for trans- TPSR A15 A14 A13 A12 A11 A10 mission of packets while the Receive Registers are used to...
  • Page 36 10 0 Internal Registers (Continued) 10 6 LOCAL DMA RECEIVE REGISTERS REMOTE BYTE COUNT REGISTERS (RBCR0 1) PAGE START AND STOP REGISTERS (PSTART PSTOP) The Page Start and Page Stop Registers program the start- RBCR1 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 ing and stopping address of the Receive Buffer Ring Since the ST-NIC uses fixed 256-byte buffers aligned on page boundaries only the upper 8 bits of the start and stop ad-...
  • Page 37 10 0 Internal Registers (Continued) cant bits of the CRC generator are latched These 6 bits are 10 10 NETWORK TALLY COUNTERS then decoded by a 1 of 64 decode to index a unique filter bit Three 8-bit counters are provided for monitoring the number (FB0 –63) in the multicast address registers If the filter bit of CRC errors Frame Alignment Errors and Missed Pack- selected is set the multicast packet is accepted The sys-...

  • Page 38: Initialization Procedures

    11 0 Initialization Procedures 12 0 Loopback Diagnostics The ST-NIC must be initialized prior to transmission or re- Three forms of local loopback are provided on the ST-NIC ception of packets from the network Power on reset is ap- The user has the ability to loopback through the deserializer plied to the ST-NIC’s reset pin This clears sets the follow- on the controller through the ENDEC module or the Trans- ing bits...

  • Page 39: Loopback Diagnostics

    12 0 Loopback Diagnostics (Continued) To initiate a loopback the user first assembles the loopback The alignment for a 64-byte packet is shown below packet then selects the type of loopback using the Transmit FIFO FIFO Configuration register bits LB0 LB1 The transmit configura- Location Contents tion register must also be set to enable or disable CRC gen-...
  • Page 40 12 0 Loopback Diagnostics (Continued) 3 Verify that the Address Recognition Logic can Path a) Recognize address match packets ST-NIC Internal b) Reject packets that fail to match an address (Note 1) LOOPBACK OPERATION IN THE ST-NIC Loopback is a modified form of transmission using only half Note 1 CDH is set CRS is not set since it is generated by the external encoder decoder of the FIFO This places certain restrictions on the use of...
  • Page 41 12 0 Loopback Diagnostics (Continued) Since errored packets can be rejected the status associat- Additional information required for network management is ed with these packets is lost unless the CPU can access the available in the Receive and Transmit Status Registers Receive Status Register before the next packer arrives In Transmit status is available after each transmission for infor- situations where another packet arrives very quickly the...

  • Page 42: Bus Arbitration And Timing

    13 0 Bus Arbitration and Timing The ST-NIC operates in three possible modes BUS MASTER (WHILE PERFORMING DMA) BUS SLAVE (WHILE BEING ACCESSED BY CPU) IDLE TL F 11157– 21 Upon power-up the ST-NIC is in an indeterminate state Af- operation After acquiring the bus in a BREQ BACK hand- ter receiving a hardware reset the ST-NIC is a bus slave in shake the Remote or Local DMA transfer is completed and...
  • Page 43 13 0 Bus Arbitration and Timing (Continued) 16-Bit Address 16-Bit Data TL F 11157 – 23 32-Bit Address 8-Bit Data TL F 11157 – 24 32-Bit Address 16-Bit Data TL F 11157 – 25 Note In 32-bit address mode ADS1 is at TRI-STATE after the first T1–T4 states thus a 4 7k pull-down resistor is required for 32-bit address...
  • Page 44 13 0 Bus Arbitration and Timing (Continued) When in 32-bit mode four additional BSCK cycles are re- FIFO BURST CONTROL quired per burst The first bus cycle (T1 – T4 ) of each burst All Local DMA transfers are burst transfers once the DMA is used to output the upper 16-bit addresses This 16-bit requests the bus and the bus is acknowledged the DMA will address is programmed in RSAR0 and RSAR1 and points to...
  • Page 45 13 0 Bus Arbitration and Timing (Continued) mine whether the packet matches its Physical Address Reg- End of Packet Processing (EOPP) times for 10 MHz and isters or maps to one of its Multicast Registers This causes 20 MHz have been tabulated in the table below the FIFO to accumulate 8 bytes Furthermore there are some synchronization delays in the DMA PLA Thus the Mode...
  • Page 46 13 0 Bus Arbitration and Timing (Continued) The FIFO at the Beginning of Transmit is the programmed FIFO threshold The next BREQ is not issued until after the ST-NIC actually begins transmitting Before transmitting the ST-NIC performs a prefetch from data i e after SFD The Transmit Prefetch diagram illus- memory to load the FIFO The number of bytes prefetched trates this process...
  • Page 47 13 0 Bus Arbitration and Timing (Continued) REMOTE DMA-BIDIRECTIONAL PORT CONTROL REMOTE READ TIMING The Remote DMA transfers data between the local buffer 1 The DMA reads byte word from local buffer memory and memory and a bidirectional port (memory to I O transfer) writes byte word into latch increments the DMA address This transfer is arbited on a byte by byte basis versus the and decrements the byte count (RBCR0 1)
  • Page 48 13 0 Bus Arbitration and Timing (Continued) REMOTE WRITE TIMING 1 ST-NIC asserts PRQ System writes byte word into latch ST-NIC removes PRQ A Remote Write operation transfers data from the I O port to the local buffer RAM The ST-NIC initiates a transfer by 2 Remote DMA reads contents of port and writes byte requesting a byte word via the PRQ The system transfers a word to local buffer memory increments address and...
  • Page 49 13 0 Bus Arbitration and Timing (Continued) An additional caution for high speed systems is that the 3 Read the Current Remote DMA Address (CRDA) (both polling must follow guidelines specified in the Time Between bytes) Chip Selects section That is there must be at least 4 bus 4 Compare to previous CRDA value if different go to 6 clocks between chip selects (For example when BSCK 5 Delay and jump to 3...
  • Page 50 13 0 Bus Arbitration and Timing (Continued) SLAVE MODE TIMING ADS0 is used to latch the address when interfacing to a multiplexed address data bus Since the ST-NIC may be a When CS is low the ST-NIC becomes a bus slave The CPU local bus master when the host CPU attempts to read or can then read or write any internal registers All register write to the controller an ACK line is used to hold off the...

  • Page 51: Preliminary Electrical Characteristics

    If Military Aerospace specified devices are required Note Absolute Maximum ratings are those values beyond please contact the National Semiconductor Sales which the safety of the device cannot be guaranteed They are not meant to imply that the device should be operated at...
  • Page 52 14 0 Preliminary Electrical Characteristics (Continued) Preliminary DC Specifications 0 C to 70 C V 5% unless otherwise specified (Continued) Symbol Parameter Conditions Units AUI INTERFACE PINS (TX and CD Diff Output Voltage (TX 78X Termination and 270X 1200 from Each to GND Diff Output Voltage Imbalance (TX 78X Termination and 270X Typical 40 mV...

  • Page 53: Switching Characteristics

    15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary Register Read (Latched Using ADS0) TL F 11157 – 33 Symbol Parameter Units Register Select Setup to ADS0 Low Register Select Hold from ADS0 Low aswi Address Strobe Width In ackdv Acknowledge Low to Data Valid Read Strobe to Data TRI-STATE (Note 3)
  • Page 54 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) Register Read (Non-Latched ADS0 TL F 11157 – 34 Symbol Parameter Units rsrs Register Select to Read Setup (Notes 1 3) rsrh Register Select Hold from Read ackdv ACK Low to Valid Data Read Strobe to Data TRI-STATE (Note 2)
  • Page 55 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) Register Write (Latched Using ADS0) TL F 11157 – 35 Symbol Parameter Units Register Select Setup to ADS0 Low Register Select Hold from ADS0 Low aswi Address Strobe Width In rwds Register Write Data Setup rwdh...
  • Page 56 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) Register Write (Non-Latched ADS0 TL F 11157 – 36 Symbol Parameter Units rsws Register Select to Write Setup (Note 1) rswh Register Select Hold from Write rwds Register Write Data Setup rwdh Register Write Data Hold...
  • Page 57 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) DMA Control Bus Arbitration TL F 11157 – 37 Symbol Parameter Units brqhl Bus Clock to Bus Request High for Local DMA brqhr Bus Clock to Bus Request High for Remote DMA brql Bus Request Low from Bus Clock backs...
  • Page 58 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) DMA Address Generation TL F 11157 – 38 Symbol Parameter Units bcyc Bus Clock Cycle Time (Note 2) Bus Clock High Time Bus Clock Low Time bcash Bus Clock to Address Strobe High bcasl Bus Clock to Address Strobe Low...
  • Page 59 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) DMA Memory Read TL F 11157 – 39 Symbol Parameter Units bcrl Bus Clock to Read Strobe Low bcrh Bus Clock to Read Strobe High Data Setup to Read Strobe High Data Hold from Read Strobe High DMA Read Strobe Width Out 2 bcyc...
  • Page 60 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) DMA Memory Write TL F 11157 – 40 Symbol Parameter Units bcwl Bus Clock to Write Strobe Low bcwh Bus Clock to Write Strobe High Data Setup to MWR High 2 bcyc Data Hold from MWR Low Write Strobe to Address TRI-STATE (Notes 1 2)
  • Page 61 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) Wait State Insertion TL F 11157 – 41 Symbol Parameter Units External Wait Setup to T3 0Clock (Note 1) External Wait Release Time (Note 1) Note 1 The addition of wait states affects the count of deserialized bytes and is limited to a number of bus clock cycles depending on the bus clock and network rates The allowable wait states are found in the table below (Assumes 10 Mbit sec data rate ) The number of allowable wait states in byte mode can be of Wait States...
  • Page 62 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) Remote DMA (Read Send Command) TL F 11157 – 42 Symbol Parameter Units bpwrl Bus Clock to Port Write Low bpwrh Bus Clock to Port Write High prqh Port Write High to Port Request High (Note 1) prql...
  • Page 63 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) Remote DMA (Read Send Command) Recovery Time TL F 11157 – 43 Symbol Parameter Units bpwrl Bus Clock to Port Write Low bpwrh Bus Clock to Port Write High prqh Port Write High to Port Request High (Note 1) prql...
  • Page 64 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) Remote DMA (Write Cycle) TL F 11157 – 44 Symbol Parameter Units bprqh Bus Clock to Port Request High (Note 1) wprql WACK to Port Request Low wackw WACK Pulse Width bprdl...
  • Page 65 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) Remote DMA (Write Cycle) Recovery Time TL F 11157 – 45 Symbol Parameter Units bprqh Bus Clock to Port Request High (Note 1) wprql WACK to Port Request Low wackw WACK Pulse Width bprdl...
  • Page 66 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) AUI Transmit Timing (End of Packet) TL F 11157 – 46 Symbol Parameter Units Transmit Output High before Idle (Half Step) Transmit Output Idle Time (Half Step) 8000 AUI TPI Receive End of Packet Timing TL F 11157 –...
  • Page 67 15 0 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) Link Pulse Timing TL F 11157 – 48 Symbol Parameter Units Time between Link Output Pulses tipw Link Integrity Output Pulse Width TPI Transmit and End of Packet Timing TL F 11157 –...

  • Page 68: Ac Timing Test Conditions

    16 0 AC Timing Test Conditions Pin Capacitance 25 C f 1 MHz All specifications are valid only if the mandatory isolation is Symbol Parameter Units employed and all differential signals are taken to be at the AUI side of the pulse transformer Input Capacitance Input Pulse Levels (TTL CMOS) GND to 3 0V...

  • Page 69: Physical Dimensions

    17 0 Physical Dimensions inches (millimeters) Plastic Chip Carrier (V) Order Number DP83902AV NS Package Number V84A 100 Pin Quad Flat Pack Order Number DP83902AVF NS Package Number VF100B...
  • Page 70 17 0 Physical Dimensions inches (millimeters) (Continued) Plastic Quad Flatpack (VJG) Order Number DP83902AVJG NS Package Number VJG100A...
  • Page 71 National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation...
  • Page 72 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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