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NXP Semiconductors MWCT1015SF Series Reference Manual (1761 pages)

Brand: NXP Semiconductors | Category: Semiconductors | Size: 17 MB

Table of Contents
3
Chapter 1 About this Manual

43
- Audience
  43
- Organization
  43
- Module Descriptions
  43
  - Example: Chip-Specific Information that Clarifies Content in the same Chapter
    44
  - Example: Chip-Specific Information that Refers to a Different Chapter
    45
- Register Descriptions
  46
- Conventions
  47
  - Notes, Cautions, and Warnings
    47
  - Numbering Systems
    47
  - Typographic Notation
    48
  - Special Terms
    48
Chapter 2 Introduction

51
- Overview
  51
- Mwct101Xs Series Introduction
  51
- Feature Summary
  52
- Block Diagram
  55
- Feature Comparison
  56
- Applications
  58
- Module Functional Categories
  58
  - Arm Cortex-M4F Core Modules
    59
  - System Modules
    60
  - Memories and Memory Interfaces
    61
  - Power Management
    62
  - Clocking
    62
  - Analog Modules
    62
  - Timer Modules
    63
  - Communication Interfaces
    64
  - Debug Modules
    64
Chapter 3 Memory Map

65
Chapter 4 Signal Multiplexing and Pin Assignment

71
- Introduction
  71
- Functional Description
  71
- Pad Description
  72
- Default Pad State
  73
- Signal Multiplexing Sheet
  74
  - IO Signal Table
    74
  - Input Muxing Table
    76
- Pinout Diagrams
  77
Chapter 5 Security Overview

79
Chapter 6 Safety Overview

89
- Introduction
  89
- Wct101Xs Safety Concept
  90
  - Cortex-M4 Structural Core Self Test (SCST)
    91
  - ECC on RAM and Flash Memory
    92
  - Power Supply Monitoring
    92
  - Clock Monitoring
    93
  - Temporal Protection
    93
  - Operational Interference Protection
    93
  - Crc
    95
  - Diversity of System Resources
    95
Chapter 7 Core Overview

97
Chapter 8 Miscellaneous Control Module (MCM)

105
System Integration Module (SIM)

131
- Chip-Specific SIM Information
  131
  - SIM Register Bitfield Implementation
    131
- Introduction
  131
  - Features
    131
- Memory Map and Register Definition
  132
  - SIM Register Descriptions
    132
Chapter 10 Port Control and Interrupts (PORT)

159
- Chip-Specific PORT Information
  159
  - Number of Pcrs
    160
  - Finding Address for Portx_Pcrn
    160
  - I/O Configuration Sequence
    160
  - Digital Input Filter Configuration Sequence
    161
  - Reset Pin Configuration
    162
- Introduction
  162
- Overview
  162
  - Features
    162
  - Modes of Operation
    163
- External Signal Description
  164
- Detailed Signal Description
  164
- Memory Map and Register Definition
  164
- Functional Description
  179
  - Pin Control
    179
  - Global Pin Control
    180
  - Global Interrupt Control
    180
  - External Interrupts
    181
  - Digital Filter
    181
Chapter 11 General-Purpose Input/Output (GPIO)

183
- Chip-Specific GPIO Information
  183
  - Instantiation Information
    183
  - GPIO Ports Memory Map
    183
  - GPIO Register Reset Values
    184
- Introduction
  184
  - Features
    184
  - Modes of Operation
    184
  - GPIO Signal Descriptions
    185
- Memory Map and Register Definition
  186
  - GPIO Register Descriptions
    186
- Functional Description
  193
  - General-Purpose Input
    193
  - General-Purpose Output
    193
Chapter 12 Crossbar Switch Lite (AXBS-Lite)

195
- Chip-Specific AXBS-Lite Information
  195
  - Crossbar Switch Master Assignments
    195
  - Crossbar Switch Slave Assignments
    195
- Introduction
  196
  - Features
    196
- Functional Description
  196
  - General Operation
    197
  - Arbitration
    197
- Initialization/Application Information
  199
Chapter 13 Memory Protection Unit (MPU)

201
- Chip-Specific MPU Information
  201
  - MPU Slave Port Assignments
    201
  - MPU Logical Bus Master Assignments
    201
  - Current PID
    202
  - Region Descriptors and Slave Port Configuration
    202
- Introduction
  202
- Overview
  203
  - Block Diagram
    203
  - Features
    204
- MPU Register Descriptions
  204
- Functional Description
  231
  - Access Evaluation Macro
    231
  - Putting It All Together and Error Terminations
    233
  - Power Management
    234
- Initialization Information
  234
- Application Information
  234
Chapter 14 Peripheral Bridge (AIPS-Lite)

237
- Chip-Specific AIPS Information
  237
  - Instantiation Information
    237
  - Memory Maps
    237
- Introduction
  238
  - Features
    238
  - General Operation
    238
- Memory Map/Register Definition
  239
  - AIPS Register Descriptions
    239
- Functional Description
  283
  - Access Support
    283
Chapter 15 Direct Memory Access Multiplexer (DMAMUX)

285
- Chip-Specific DMAMUX Information
  285
  - Number of Channels
    285
  - DMA Transfers Via TRGMUX Trigger
    285
- Introduction
  285
  - Overview
    286
  - Features
    286
  - Modes of Operation
    287
- Memory Map/Register Definition
  287
  - DMAMUX Register Descriptions
    287
- Functional Description
  289
- Initialization/Application Information
  293
  - Reset
    293
  - Enabling and Configuring Sources
    293
Chapter 16 Enhanced Direct Memory Access (Edma)

297
- Chip-Specific Edma Information
  297
  - Number of Channels
    297
- Introduction
  297
  - Edma System Block Diagram
    298
  - Block Parts
    298
  - Features
    299
- Modes of Operation
  301
- Memory Map/Register Definition
  301
  - TCD Memory
    301
  - TCD Initialization
    302
  - TCD Structure
    302
  - Reserved Memory and Bit Fields
    302
  - DMA Register Descriptions
    302
- Functional Description
  351
  - Edma Basic Data Flow
    351
  - Fault Reporting and Handling
    354
  - Channel Preemption
    357
- Initialization/Application Information
  357
  - Edma Initialization
    357
  - Programming Errors
    359
  - Arbitration Mode Considerations
    360
  - Performing DMA Transfers
    360
  - Monitoring Transfer Descriptor Status
    364
  - Channel Linking
    366
  - Dynamic Programming
    367
  - Suspend/Resume a DMA Channel with Active Hardware Service Requests
    371
Chapter 17 Trigger MUX Control (TRGMUX)

373
- Chip-Specific TRGMUX Information
  373
  - Module Interconnectivity
    373
  - Chip-Specific TRGMUX Registers
    377
- Introduction
  377
- Features
  377
- Memory Map and Register Definition
  378
  - TRGMUX Register Descriptions
    378
Chapter 18 External Watchdog Monitor (EWM)

417
- Chip-Specific EWM Information
  417
  - EWM_OUT Signal Configuration
    417
  - EWM Memory Map Access
    417
  - EWM Low-Power Modes
    417
- Introduction
  418
  - Features
    418
  - Modes of Operation
    419
  - Block Diagram
    420
- EWM Signal Descriptions
  420
- Memory Map/Register Definition
  421
  - EWM Register Descriptions
    421
- Functional Description
  426
  - The Ewm_Out_B Signal
    426
  - Ewm_Out_B Pin State in Low Power Modes
    427
  - The Ewm_In Signal
    427
  - EWM Counter
    428
  - EWM Compare Registers
    428
  - EWM Refresh Mechanism
    428
  - EWM Interrupt
    429
  - Counter Clock Prescaler
    429
Chapter 19 Error Injection Module (EIM)

431
- Chip-Specific EIM Information
  431
  - EIM Channel Assignments
    431
- Introduction
  431
  - Overview
    432
  - Features
    433
- EIM Register Descriptions
  433
- Functional Description
  441
  - Error Injection Scenarios
    441
Chapter 20 Error Reporting Module (ERM)

443
- Chip-Specific ERM Information
  443
  - Sources of Memory Error Events
    443
- Introduction
  443
  - Overview
    443
  - Features
    444
- ERM Register Descriptions
  444
  - ERM Memory Map
    444
  - ERM Configuration Register 0 (CR0)
    445
  - ERM Status Register 0 (SR0)
    447
  - ERM Memory N Error Address Register (EAR0 - EAR1)
    449
- Functional Description
  450
  - Single-Bit Correction Events
    450
  - Non-Correctable Error Events
    451
- Initialization
  452
Chapter 21 Watchdog Timer (WDOG)

453
- Chip-Specific WDOG Information
  453
  - WDOG Clocks
    453
  - WDOG Low-Power Modes
    453
  - Default Watchdog Timeout
    454
  - Watchdog Timeout Reaction
    454
- Introduction
  455
  - Features
    455
  - Block Diagram
    456
- Memory Map and Register Definition
  456
  - WDOG Register Descriptions
    456
- Functional Description
  463
  - Clock Source
    463
  - Watchdog Refresh Mechanism
    464
  - Configuring the Watchdog
    466
  - Using Interrupts to Delay Resets
    467
  - Backup Reset
    467
  - Functionality in Debug and Low-Power Modes
    468
  - Fast Testing of the Watchdog
    468
- Application Information
  470
  - Disable Watchdog
    470
  - Disable Watchdog after Reset
    470
  - Configure Watchdog
    471
  - Refreshing the Watchdog
    471
Chapter 22 Cyclic Redundancy Check (CRC)

473
- Chip-Specific CRC Information
  473
- Introduction
  473
  - Features
    473
  - Block Diagram
    474
  - Modes of Operation
    474
- Memory Map and Register Descriptions
  474
  - CRC Register Descriptions
    474
- Functional Description
  479
  - CRC Initialization/Reinitialization
    479
  - CRC Calculations
    479
  - Transpose Feature
    480
  - CRC Result Complement
    482
Chapter 23 Reset and Boot

483
- Introduction
  483
- Reset
  483
  - Power-On Reset (POR)
    484
  - System Reset Sources
    484
  - MCU Resets
    488
  - Reset Pin
    489
  - Debug Resets
    489
- Boot
  490
  - Boot Sources
    490
  - FOPT Boot Options
    490
  - Boot Sequence
    491
Chapter 24 Reset Control Module (RCM)

493
Chapter 25 Clock Distribution

509
- Introduction
  509
- High Level Clocking Diagram
  509
- Clock Definitions
  510
- Internal Clocking Requirements
  512
  - Clock Divider Values after Reset
    516
  - HSRUN Mode Clocking
    516
  - VLPR Mode Clocking
    516
  - VLPR/VLPS Mode Entry
    516
- Clock Gating
  517
- Module Clocks
  517
Chapter 26 System Clock Generator (SCG)

529
Chapter 27 Chip-Specific PCC Information

565
- Features
  566
- Functional Description
  567
- PCC FTFC Register (PCC_FTFC)
  569
- PCC DMAMUX Register (PCC_DMAMUX)
  570
- PCC Flexcan0 Register (Pcc_Flexcan0)
  572
- PCC Flexcan1 Register (Pcc_Flexcan1)
  573
- PCC FTM3 Register (PCC_FTM3)
  575
- PCC ADC1 Register (PCC_ADC1)
  576
- PCC Flexcan2 Register (Pcc_Flexcan2)
  578
- PCC LPSPI0 Register (PCC_LPSPI0)
  579
- PCC LPSPI1 Register (PCC_LPSPI1)
  581
- PCC LPSPI2 Register (PCC_LPSPI2)
  582
- PCC PDB1 Register (PCC_PDB1)
  584
- PCC CRC Register (PCC_CRC)
  586
- PCC PDB0 Register (PCC_PDB0)
  587
- PCC LPIT Register (PCC_LPIT)
  589
- PCC FTM0 Register (PCC_FTM0)
  590
- PCC FTM1 Register (PCC_FTM1)
  592
- PCC FTM2 Register (PCC_FTM2)
  593
- PCC ADC0 Register (PCC_ADC0)
  595
- PCC RTC Register (PCC_RTC)
  597
- PCC LPTMR0 Register (PCC_LPTMR0)
  598
- PCC PORTA Register (PCC_PORTA)
  600
- PCC PORTB Register (PCC_PORTB)
  602
- PCC PORTC Register (PCC_PORTC)
  603
- PCC PORTD Register (PCC_PORTD)
  605
- PCC PORTE Register (PCC_PORTE)
  606
- PCC Flexio Register (Pcc_Flexio)
  608
- PCC EWM Register (PCC_EWM)
  609
- PCC LPI2C0 Register (PCC_LPI2C0)
  611
- PCC LPI2C1 Register (PCC_LPI2C1)
  612
- PCC LPUART0 Register (PCC_LPUART0)
  614
- PCC LPUART1 Register (PCC_LPUART1)
  615
- PCC LPUART2 Register (PCC_LPUART2)
  617
- PCC FTM4 Register (PCC_FTM4)
  619
- PCC FTM5 Register (PCC_FTM5)
  620
- PCC FTM6 Register (PCC_FTM6)
  622
- PCC FTM7 Register (PCC_FTM7)
  624
- PCC CMP0 Register (PCC_CMP0)
  625
- PCC QSPI Register (PCC_QSPI)
  627
Chapter 28 Memories and Memory Interfaces

629
- Introduction
  629
- Flash Memory Controller and Flash Memory Modules
  629
- SRAM Configuration
  629
  - SRAM Sizes
    630
  - SRAM Accessibility
    631
  - SRAM Arbitration and Priority Control
    632
Chapter 29 Chip-Specific LMEM Information

635
- Block Diagram
  636
- Cache Features
  637
- Functional Description
  648
- SRAM Function
  649
- Cache Function
  651
- Cache Control
  652
Chapter 30

657
- Chip-Specific MSCM Information
  657
- Overview
  658
- MSCM Memory Map/Register Definition
  659
Chapter 31

691
- Chip-Specific FMC Information
  691
  - FMC Masters
    692
  - Modes of Operation
    693
  - Default Configuration
    694
  - Initialization and Application Information
    695
- Chip-Specific FTFC Information
  697
Chapter 32

698
- Flash Memory Types
  698
- Flash Memory Map
  708
- Flash Memory Security
  709
- Simultaneous Operations on PFLASH Read Partitions
  710
  - Features
    711
  - Block Diagram
    713
  - External Signal Description
    716
- Program Flash 0 IFR Map
  717
  - Register Descriptions
    718
  - Functional Description
    736
- Flexnvm Description
  738
- Interrupts
  741
- Flash Operation in Low-Power Modes
  742
- Read While Write (RWW)
  743
- FTFC Command Operations
  744
- Margin Read Commands
  750
- Flash Command Descriptions
  751
- Security
  777
- Cryptographic Services Engine (Csec)
  779
- Reset Sequence
  817
Chapter 33 Chip-Specific Quadspi Information

819
- Use Case
  820
- External Memory Options
  821
- Recommended Programming Sequence
  822
- Quadspi_Soccr[Soccfg] Implementation
  823
- Introduction
  825
  - Block Diagram
    826
  - Quadspi Modes of Operation
    827
  - Acronyms and Abbreviations
    828
  - Glossary for Quadspi Module
    829
  - External Signal Description
    830
  - Driving External Signals
    831
  - Memory Map and Register Definition
    833
  - Peripheral Bus Register Descriptions
    834
  - Serial Flash Address Assignment
    878
- Flash Memory Mapped AMBA Bus
  879
- Interrupt Signals
  884
- Functional Description
  885
  - Hyperram Support
    904
  - Initialization/Application Information
    905
  - Flash Device Selection
    908
- Byte Ordering - Endianness
  912
  - Programming Flash Data
    913
  - Reading Flash Data into the AHB Buffer
    914
- Driving Flash Control Signals in Single and Dual Mode
  915
- Sampling of Serial Flash Input Data
  921
  - Supported Read Modes
    922
  - Data Strobe (DQS) Sampling Method
    925
- Data Input Hold Requirement of Flash
  928
- Introduction
  929
Chapter 34

930
- Entering and Exiting Power Modes
  930
- Clocking Modes
  931
  - Compute Operation (CPO)
    933
  - Peripheral Doze
    934
  - Power Mode Transitions
    935
- Shutdown Sequencing for Power Modes
  936
- Quadspi Operation
  940
  - Introduction
    941
  - Memory Map and Register Descriptions
    943
Chapter 35

944
- SMC Parameter Register (SMC_PARAM)
  944
- Power Mode Protection Register (SMC_PMPROT)
  945
- Power Mode Control Register (SMC_PMCTRL)
  947
- Stop Control Register (SMC_STOPCTRL)
  949
- Power Mode Status Register (SMC_PMSTAT)
  950
- Functional Description
  951
- Power Mode Entry/Exit Sequencing
  952
- Run Modes
  955
- Stop Modes
  957
- Debug in Low Power Modes
  958
Chapter 36 Chip-Specific PMC Information

961
- Modes of Operation
  962
- Low Voltage Reset (LVR) Operation
  963
- PMC Register Descriptions
  964
- Instantiation Information
  971
Chapter 37 ADC Connections/Channel Assignment

972
- DMA Support on ADC
  973
- ADC Internal Supply Monitoring
  974
- ADC Trigger Sources
  975
  - PDB Triggering Scheme
    977
  - TRGMUX Trigger Scheme
    978
- Trigger Latching and Arbitration
  979
- ADC Triggering Configurations
  981
- ADC Low-Power Modes
  988
- ADC Calibration Scheme
  990
Chapter 38

993
Chapter 39

1048
- CMP External References
  1048
- CMP Trigger Mode
  1049
  - Introduction
    1050
  - Features
    1051
- Bit DAC Key Features
  1052
- CMP Block Diagram
  1053
- CMP Pin Descriptions
  1055
- CMP Functional Modes
  1056
  - Disabled Mode (# 1)
    1057
    
    Continuous Mode (#S 2A & 2B)
    1058
    
    Sampled, Filtered Mode (#S 4A & 4B)
    1060
    
    Windowed Mode (#S 5A & 5B)
    1062
  - Windowed/Filtered Mode (#7)
    1065
- Memory Map/Register Definitions
  1066
  - CMP Control Register 1 (Cmpx_C1)
    1070
  - CMP Control Register 2 (Cmpx_C2)
    1073
- CMP Functional Description
  1075
  - Low-Pass Filter
    1076
  - Interrupts
    1078
- DAC Functional Description
  1079
  - DAC Clocks
    1080
- Chip-Specific PDB Information
  1083
Chapter 40

1084
- PDB Trigger Interconnections with ADC and TRGMUX
  1084
- Pulse-Out Enable Register Implementation
  1091
- Implementation
  1092
  - Block Diagram
    1093
  - Modes of Operation
    1094
- Status and Control Register (Pdbx_Sc)
  1098
- Modulus Register (Pdbx_Mod)
  1101
- Interrupt Delay Register (Pdbx_Idly)
  1102
- Channel N Status Register (Pdbx_Chns)
  1103
- Channel N Delay 0 Register (Pdbx_Chndly0)
  1104
- Channel N Delay 1 Register (Pdbx_Chndly1)
  1105
- Channel N Delay 3 Register (Pdbx_Chndly3)
  1106
- Channel N Delay 4 Register (Pdbx_Chndly4)
  1107
- Channel N Delay 6 Register (Pdbx_Chndly6)
  1108
- Channel N Delay 7 Register (Pdbx_Chndly7)
  1109
- Pulse-Out N Delay Register (Pdbx_Pondly)
  1110
- PDB Trigger Input Source Selection
  1113
- Updating the Delay Registers
  1114
- Interrupts
  1116
- Impact of Using the Prescaler and Multiplication Factor on Timing Resolution
  1117
Chapter 41 Chip-Specific FTM Information

1119
- FTM Interrupts
  1120
  - FTM Hardware Triggers and Synchronization
    1121
  - FTM Input Capture Options
    1124
  - FTM Modulation Implementation
    1125
  - FTM Global Time Base
    1126
    
    Introduction
    1127
    
    Modes of Operation
    1129
- FTM Signal Descriptions
  1131
  - Register Descriptions
    1132
  - Functional Description
    1189
- Prescaler
  1190
- Channel Modes
  1196
- Input Capture Mode
  1198
- Output Compare Mode
  1203
- Edge-Aligned PWM (EPWM) Mode
  1204
- Center-Aligned PWM (CPWM) Mode
  1206
- Combine Mode
  1208
- Modified Combine PWM Mode
  1216
- Complementary Mode
  1220
- Registers Updated from Write Buffers
  1221
- PWM Synchronization
  1223
- Inverting
  1238
- Software Output Control Mode
  1239
- Deadtime Insertion
  1241
- Output Mask
  1245
- Fault Control
  1246
- Polarity Control
  1250
- Initialization
  1251
- External Trigger
  1252
- Initialization Trigger
  1253
- Capture Test Mode
  1256
- Dual Edge Capture Mode
  1257
  - Quadrature Decoder Mode
    1265
  - Debug Mode
    1271
  - Reload Points
    1272
  - Global Load
    1275
  - Global Time Base (GTB)
    1276
  - Channel Trigger Output
    1277
  - External Control of Channels Output
    1278
- Reset Overview
  1289
  - FTM Interrupts
    1291
  - Initialization Procedure
    1292
- Chip-Specific LPIT Information
  1295
Chapter 42

1296
- LPIT Input Triggers
  1296
  - Introduction
    1297
  - Block Diagram
    1299
  - Modes of Operation
    1300
  - Memory Map and Registers
    1301
  - Functional Description
    1317
  - Initialization
    1319
- Timer Modes
  1320
- Channel Chaining
  1321
- Detailed Timing
  1322
Chapter 43

1335
- Chip-Specific LPTMR Information
  1335
- Introduction
  1336
- LPTMR Signal Descriptions
  1337
  - LPTMR Register Descriptions
    1338
  - Functional Description
    1343
  - LPTMR Prescaler/Glitch Filter
    1344
  - LPTMR Counter
    1345
  - LPTMR Compare
    1346
Chapter 44

1349
- Chip-Specific RTC Information
  1349
  - Multiple Trigger
    1350
    
    Register Definition
    1351
    
    Functional Description
    1361
  - Time Counter
    1362
  - Compensation
    1363
  - Time Alarm
    1364
  - Interrupt
    1365
Chapter 45

1367
- Chip-Specific LPSPI Information
  1367
  - Introduction
    1368
  - Features
    1370
  - Block Diagram
    1371
  - Signal Descriptions
    1372
  - Memory Map and Registers
    1374
  - Functional Description
    1397
  - Master Mode
    1398
  - Slave Mode
    1404
    
    Interrupts and DMA Requests
    1406
    
    Peripheral Triggers
    1407
Chapter 46 Chip-Specific LPI2C Information

1409
- Introduction
  1410
- Features
  1411
- Block Diagram
  1413
- Signal Descriptions
  1414
- Memory Map and Registers
  1415
- LPI2C Register Descriptions
  1416
- Functional Description
  1454
- Clocking and Resets
  1455
- Slave Mode
  1461
- Interrupts and DMA Requests
  1463
- Peripheral Triggers
  1466
Chapter 47

1467
- Chip-Specific LPUART Information
  1467
  - Introduction
    1468
  - Modes of Operation
    1469
- Register Definition
  1471
  - Functional Description
    1497
  - Baud Rate Generation
    1498
  - Receiver Functional Description
    1502
  - Additional LPUART Functions
    1508
  - Infrared Interface
    1510
  - Interrupts and Status Flags
    1511
  - Peripheral Triggers
    1512
Chapter 48

1515
- Chip-Specific Flexio Information
  1515
  - Features
    1516
  - Modes of Operation
    1517
- Memory Map and Registers
  1518
  - Functional Description
    1542
  - Shifter Operation
    1543
  - Timer Operation
    1545
  - Pin Operation
    1549
    
    Interrupts and DMA Requests
    1550
    
    Application Information
    1551
  - UART Receive
    1552
  - SPI Master
    1554
  - SPI Slave
    1556
  - I2C Master
    1558
  - I2S Master
    1559
  - I2S Slave
    1561
- Chip-Specific Flexcan Information
  1563
Chapter 49

1564
- Flexcan External Time Tick
  1564
- Flexcan Oscillator Clock
  1565
  - Introduction
    1567
  - Overview
    1568
  - Modes of Operation
    1570
- Flexcan Signal Descriptions
  1572
  - CAN Register Descriptions
    1574
  - Flexcan Memory Partition for CAN FD
    1651
  - Flexcan Message Buffer Memory Map
    1652
  - Rx FIFO Structure
    1654
  - Functional Description
    1657
  - Arbitration Process
    1659
  - Receive Process
    1662
  - Matching Process
    1664
  - Receive Process under Pretended Networking Mode
    1669
  - Move Process
    1673
  - Data Coherence
    1675
  - Rx FIFO
    1677
  - CAN Protocol Related Features
    1681
  - Clock Domains and Restrictions
    1701
    
    Modes of Operation Details
    1705
    
    Interrupts
    1708
  - Bus Interface
    1710
    
    Initialization/Application Information
    1711
    
    Introduction
    1713
- CM4 ROM Table
  1715
- Debug Port
  1716
- Debug Port Pin Descriptions
  1717
- MDM-AP Status and Control Registers
  1718
  - MDM-AP Control Register
    1719
  - MDM-AP Status Register
    1720
  - Debug Resets
    1721
- Ahb-Ap
  1722
- Core Trace Connectivity
  1723
- Debug in Low-Power Modes
  1724
  - Debug Module State in Low-Power Modes
    1725
Chapter 51

1727
- Chip-Specific JTAGC Information
  1727
- Features
  1728
- External Signal Description
  1730
- Test Mode Select (TMS)
  1731
- Device Identification Register
  1732
- Boundary Scan Register
  1733
- TAP Controller State Machine
  1734
- JTAGC Block Instructions
  1736
- Boundary Scan
  1739

NXP Semiconductors Categories

Motherboard Microcontrollers Computer Hardware Control Unit Controller

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NXP Semiconductors MWCT1015SF Series Manuals

NXP Semiconductors MWCT1015SF Series Reference Manual (1761 pages)

Table of Contents

Chapter 1 About this Manual

Chapter 2 Introduction

Chapter 3 Memory Map

Chapter 4 Signal Multiplexing and Pin Assignment

Chapter 5 Security Overview

Chapter 6 Safety Overview

Chapter 7 Core Overview

Chapter 8 Miscellaneous Control Module (MCM)

System Integration Module (SIM)

Chapter 10 Port Control and Interrupts (PORT)

Chapter 11 General-Purpose Input/Output (GPIO)

Chapter 12 Crossbar Switch Lite (AXBS-Lite)

Chapter 13 Memory Protection Unit (MPU)

Chapter 14 Peripheral Bridge (AIPS-Lite)

Chapter 15 Direct Memory Access Multiplexer (DMAMUX)

Chapter 16 Enhanced Direct Memory Access (Edma)

Chapter 17 Trigger MUX Control (TRGMUX)

Chapter 18 External Watchdog Monitor (EWM)

Chapter 19 Error Injection Module (EIM)

Chapter 20 Error Reporting Module (ERM)

Chapter 21 Watchdog Timer (WDOG)

Chapter 22 Cyclic Redundancy Check (CRC)

Chapter 23 Reset and Boot

Chapter 24 Reset Control Module (RCM)

Chapter 25 Clock Distribution

Chapter 26 System Clock Generator (SCG)

Chapter 27 Chip-Specific PCC Information

Chapter 28 Memories and Memory Interfaces

Chapter 29 Chip-Specific LMEM Information

Chapter 30

Chapter 31

Chapter 32

Chapter 33 Chip-Specific Quadspi Information

Chapter 34

Chapter 35

Chapter 36 Chip-Specific PMC Information

Chapter 37 ADC Connections/Channel Assignment

Chapter 38

Chapter 39

Chapter 40

Chapter 41 Chip-Specific FTM Information

Chapter 42

Chapter 43

Chapter 44

Chapter 45

Chapter 46 Chip-Specific LPI2C Information

Chapter 47

Chapter 48

Chapter 49

Chapter 51

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