Table of Contents
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FeaTures
Measures Up to 12 Battery Cells in Series
n
Stackable Architecture Supports 100s of Cells
n
Built-In isoSPI™ Interface:
n
1Mbps Isolated Serial Communications
Uses a Single Twisted Pair, Up to 100 Meters
Low EMI Susceptibility and Emissions
1.2mV Maximum Total Measurement Error
n
290µs to Measure All Cells in a System
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Synchronized Voltage and Current Measurement
n
16-Bit Delta-Sigma ADC with Frequency Program-
n
mable 3rd Order Noise Filter
Engineered for ISO26262 Compliant Systems
n
Passive Cell Balancing with Programmable Timer
n
5 General Purpose Digital I/O or Analog Inputs:
n
Temperature or other Sensor Inputs
Configurable as an I
4μA Sleep Mode Supply Current
n
48-Lead SSOP Package
n
applicaTions
Electric and Hybrid Electric Vehicles
n
Backup Battery Systems
n
Grid Energy Storage
n
High Power Portable Equipment
n
Typical applicaTion
+
LTC6804-1
12S1P
+
+
LTC6804-1
+
+
LTC6804-1
+
2
C or SPI Master
IPB
IMB
IPA
ILP
IMA
•
•
IPB
IMB
IPA
IMA
•
•
IPB
IMB
IPA
IMA
For more information
LTC6804-1/LTC6804-2
Multicell Battery Monitors
DescripTion
The
LTC
6804
is a 3rd generation multicell battery stack
®
monitor that measures up to 12 series connected battery
cells with a total measurement error of less than 1.2mV. The
cell measurement range of 0V to 5V makes the LTC6804
suitable for most battery chemistries. All 12 cell voltages
can be captured in 290µs, and lower data acquisition rates
can be selected for high noise reduction.
Multiple LTC6804 devices can be connected in series,
permitting simultaneous cell monitoring of long, high volt-
age battery strings. Each LTC6804 has an isoSPI interface
for high speed, RF-immune, local area communications.
Using the LTC6804-1, multiple devices are connected in
a daisy-chain with one host processor connection for all
devices. Using the LTC6804-2, multiple devices are con-
nected in parallel to the host processor, with each device
individually addressed.
Additional features include passive balancing for each cell,
an onboard 5V regulator, and 5 general purpose I/O lines.
In sleep mode, current consumption is reduced to 4µA.
The LTC6804 can be powered directly from the battery,
or from an isolated supply.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered and isoSPI is a
trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. patents, including 8908799, 9182428, 9270133.
Total Measurement Error
vs Temperature of 5 Typical Units
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
MPU
–50
SPI
IP
LTC6820
IM
680412 TA01a
www.linear.com/LTC6804-1
CELL VOLTAGE = 3.3V
5 TYPICAL UNITS
–25
0
25
50
75
100
125
TEMPERATURE (°C)
680412 TA01b
680412fc
1
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Related Manuals for Linear Technology LTC6804-1
Summary of Contents for Linear Technology LTC6804-1
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Page 1: Features
Backup Battery Systems L, LT, LTC, LTM, Linear Technology and the Linear logo are registered and isoSPI is a Grid Energy Storage trademark of Linear Technology Corporation. All other trademarks are the property of their High Power Portable Equipment respective owners. -
Page 2: Table Of Contents
LTC6804-1/LTC6804-2 Table oF conTenTs Features ............. 1 Data Link Layer ............44 Applications ..........1 Network Layer ............44 Typical Application ........1 Programming Examples .........54 Description..........1 Simple Linear Regulator .........58 Absolute Maximum Ratings ......3 Improved Regulator Power Efficiency .....58 Pin Configuration .......... -
Page 3: Absolute Maximum Ratings
LTC6804-1/LTC6804-2 absoluTe MaxiMuM raTings (Note 1) – Total Supply Voltage V to V ........75V C8 to C4 ..........–0.3V to 25V – Input Voltage (Relative to V C4 to C0 ..........–0.3V to 25V C0 ............–0.3V to 0.3V Current In/Out of Pins C12 ............ -
Page 4: Order Information
LTC6804-1/LTC6804-2 orDer inForMaTion http://www.linear.com/product/LTC6804-1#orderinfo TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6804IG-1#PBF LTC6804IG-1#TRPBF LTC6804G-1 48-Lead Plastic SSOP –40°C to 85°C LTC6804HG-1#PBF LTC6804HG-1#TRPBF LTC6804G-1 48-Lead Plastic SSOP –40°C to 125°C LTC6804IG-2#PBF LTC6804IG-2#TRPBF LTC6804G-2 48-Lead Plastic SSOP –40°C to 85°C... - Page 5 LTC6804-1/LTC6804-2 elecTrical characTerisTics denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. The test conditions are V = 39.6V, V = 5.0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS UNITS – Total Measurement Error (TME) in C(n) to C(n –...
- Page 6 Supply Current if LTC6804-2: ISOMD = 1, READY REG(isoSPI) isoSPI in READY/ACTIVE States = 2k ACTIVE Note: ACTIVE State Current LTC6804-1: ISOMD = 0, READY Assumes t = 1µs, (Note 3) = 2k ACTIVE LTC6804-1: ISOMD = 1, READY = 2k ACTIVE 10.2...
- Page 7 LTC6804-1/LTC6804-2 elecTrical characTerisTics denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. The test conditions are V = 39.6V, V = 5.0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS UNITS Supply Voltage...
- Page 8 LTC6804-1/LTC6804-2 elecTrical characTerisTics denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. The test conditions are V = 39.6V, V = 5.0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS UNITS Digital Input Current Pins CSB, SCK, SDI, ISOMD, SWTEN, ±1...
- Page 9 LTC6804-1/LTC6804-2 elecTrical characTerisTics denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. The test conditions are V = 39.6V, V = 5.0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS UNITS isoSPI Timing Specifications (See Figure 19)
- Page 10 LTC6804-1/LTC6804-2 Typical perForMance characTerisTics = 25°C, unless otherwise noted. Measurement Error Measurement Error Due to IR Measurement Error Long- vs Temperature Reflow Term Drift 260°C, 1 CYCLE CELL VOLTAGE = 3.3V CELL VOLTAGE = 3.3V 8 TYPICAL PARTS 5 TYPICAL UNITS –0.5...
- Page 11 LTC6804-1/LTC6804-2 Typical perForMance characTerisTics = 25°C, unless otherwise noted. Measurement Gain Error Measurement Gain Error Hysteresis, Hot Hysteresis, Cold Noise Filter Response = 85°C TO 25°C = –45°C TO 25°C –10 –20 –30 –40 –50 –60 –70 –10 –50 –40 –30 –20...
- Page 12 LTC6804-1/LTC6804-2 Typical perForMance characTerisTics = 25°C, unless otherwise noted. Cell Measurement Error Cell Measurement CMRR vs Common Mode Voltage vs Frequency Measurement Error vs V C12-C11 = 3.3V = 5V MEASUREMENT ERROR OF CM(IN) NORMAL MODE CONVERSIONS = 39.6V –10 CELL 1 WITH 3.3V INPUT.
- Page 13 LTC6804-1/LTC6804-2 Typical perForMance characTerisTics = 25°C, unless otherwise noted. vs Temperature Load Regulation Line Regulation REF2 REF2 REF2 3.003 = 39.6V GENERATED FROM 5 TYPICAL PARTS DRIVE PIN, FIGURE 28 3.002 –200 3.001 –400 3.000 –600 = 39.6V –50 2.999 = 5V –100...
- Page 14 LTC6804-1/LTC6804-2 Typical perForMance characTerisTics = 25°C, unless otherwise noted. Discharge Switch On-Resistance vs Cell Voltage Drive Pin Load Regulation Drive Pin Line Regulation ON-RESISTANCE OF INTERNAL = 39.6V DISCHARGE SWITCH MEASURED WITH 100 . EXTERNAL DISCHARGE –20 RESISTOR BETWEEN S(n) and C(n) –40...
- Page 15 LTC6804-1/LTC6804-2 Typical perForMance characTerisTics = 25°C, unless otherwise noted. isoSPI Driver Current Gain Voltage vs Temperature Voltage Load Regulation (Port A/PortB) vs Bias Current BIAS BIAS 2.010 2.02 = 1mA 3 PARTS 2.01 2.005 2.000 2.00 1.99 1.995 = 0.5V = 1.0V...
- Page 16 LTC6804-1/LTC6804-2 Typical perForMance characTerisTics = 25°C, unless otherwise noted. Write Command to a Daisy-Chained Write Command to a Daisy-Chained Device (ISOMD = 0) Device (ISOMD = 1) 5V/DIV IPA-IMA 1V/DIV 5V/DIV (PORT A) PORT A 5V/DIV 5V/DIV IPB-IMB 1V/DIV IPB-IMB...
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Page 17: Pin Functions
LTC6804-1/LTC6804-2 pin FuncTions C0 to C12: Cell Inputs. Serial Port Pins S1 to S12: Balance Inputs/Outputs. 12 N-MOSFETs are LTC6804-1 LTC6804-2 (DAISY-CHAINABLE) (ADDRESSABLE) connected between S(n) and C(n – 1) for discharging cells. – – ISOMD = V ISOMD = V... -
Page 18: Block Diagram
LTC6804-1/LTC6804-2 block DiagraM LTC6804-1 ICMP REGD IBIAS 6-CELL ADC2 SDO/(NC) SERIAL I/O PORT B – SDI/(NC) LOGIC DIGITAL FILTERS MEMORY SCK/(IPA) SERIAL I/O 6-CELL PORT A ADC1 CSB/(IMA) – ISOMD DRIVE 12 BALANCE FETs S(n) REGD SWTEN C(n – 1) - Page 19 LTC6804-1/LTC6804-2 block DiagraM LTC6804-2 REGD 6-CELL ADC2 SDO/(IBIAS) SERIAL I/O ADDRESS – SDI/(ICMP) LOGIC DIGITAL FILTERS MEMORY SCK/(IPA) SERIAL I/O 6-CELL PORT A ADC1 CSB/(IMA) – ISOMD DRIVE 12 BALANCE FETs S(n) REGD SWTEN C(n – 1) SOFTWARE TIMER REF1...
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Page 20: Operation
LTC6804-1/LTC6804-2 operaTion STATE DIAGRAM returns to the SLEEP state. If the software discharge timer is disabled, only the watchdog timer is relevant. The operation of the LTC6804 is divided into two separate sections: the core circuit and the isoSPI circuit. Both sec-... -
Page 21: Isospi State Descriptions
DRIVE output pin. Alternatively, V can be powered by an external supply. Note: The LTC6804-1 has two isoSPI ports (A and B), for daisy-chain communication. The LTC6804-2 has only one The power consumption varies according to the opera- isoSPI port (A), for parallel-addressable communication. - Page 22 LTC6804-1/LTC6804-2 operaTion Table 2. isoSPI Supply Current Equations ISOMD isoSPI STATE DEVICE CONNECTION REG(isoSPI) IDLE LTC6804-1/LTC6804-2 READY LTC6804-1 2.8mA + 5 • I Note: I = V + R BIAS – 1.6mA + 3 • I LTC6804-2 1.8mA + 3 • I –...
- Page 23 LTC6804-1/LTC6804-2 operaTion The conversion times for these modes are provided in NORMAL MODE Table 5. If the core is in STANDBY state, an additional FILTERED MODE time is required to power up the reference before REFUP beginning the ADC conversions. The reference can remain...
- Page 24 LTC6804-1/LTC6804-2 operaTion Measuring Cell Voltages (ADCV Command) REFUP The ADCV command initiates the measurement of the SERIAL ADCV + PEC INTERFACE battery cell inputs, pins C0 through C12. This command MEASURE CALIBRATE ADC2 has options to select the number of channels to measure...
- Page 25 LTC6804-1/LTC6804-2 operaTion Under/Overvoltage Monitoring by connecting the temperature sensors to the GPIOs. These sensors can be powered from the 2nd reference Whenever the C inputs are measured, the results are com- which is also measured by the ADAX command, resulting pared to undervoltage and overvoltage thresholds stored in precise ratiometric measurements.
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Page 26: Data Acquisition System Diagnostics
LTC6804-1/LTC6804-2 operaTion CYCLE REFUP SKEW1 SKEW1 SERIAL ADCVAX + PEC INTERFACE MEASURE MEASURE MEASURE MEASURE MEASURE MEASURE ADC2 CALIBRATE C7 TO C6 C8 TO C7 C9 TO C8 C10 TO C9 C11 TO C10 C12 TO C11 MEASURE MEASURE MEASURE... - Page 27 LTC6804-1/LTC6804-2 operaTion Table 9 shows the conversion time of the ADSTAT com- Issuing an ADSTAT command with CHST = 100 runs an mand measuring all 4 internal parameters. t indicates ADC measurement of just the digital supply (V ). This REGD the total conversion time for the ADSTAT command.
- Page 28 LTC6804-1/LTC6804-2 operaTion test. The MUXFAIL bit is also set to 1 on power-up (POR) test signal passes through the digital filter and is con- or after a CLRSTAT command. verted to a 16-bit value. The 1-bit test signal undergoes the same digital conversion as the regular 1-bit pulse The DIAGN command takes about 400µs to complete if the...
- Page 29 LTC6804-1/LTC6804-2 operaTion The CLRAUX command clears auxiliary register group time to create a large enough difference for the algorithm A and B. All bytes in these registers are set to 0xFF by to detect an open connection. This can be accomplished CLRAUX command.
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Page 30: Watchdog And Software Discharge Timer
LTC6804-1/LTC6804-2 operaTion Thermal Shutdown WATCHDOG AND SOFTWARE DISCHARGE TIMER To protect the LTC6804 from overheating, there is a thermal When there is no wake-up signal (see Figure 21) for more shutdown circuit included inside the IC. If the temperature than 2 seconds, the watchdog timer expires. This resets detected on the die goes above approximately 150°C, the... -
Page 31: I 2 C/Spi Master On Ltc6804 Using Gpios
CFG register group so these ports are not pulled low internally by the device. C/SPI MASTER ON LTC6804 USING GPIOS The I/O ports GPIO3, GPIO4 and GPIO5 on LTC6804-1 and COMM Register LTC6804-2 can be used as an I C or SPI master port to LTC6804 has a 6-byte COMM register as shown in Table 15. - Page 32 LTC6804-1/LTC6804-2 operaTion Table 16. Write Codes for ICOMn[3:0] and FCOMn[3:0] on I C Master CONTROL BITS CODE ACTION DESCRIPTION 0110 START Generate a START Signal on I C Port Followed By Data Transmission 0001 STOP Generate a STOP Signal on I...
- Page 33 LTC6804-1/LTC6804-2 operaTion Any number of bytes can be transmitted to the slave in RDCOMM Command: The data received from the slave groups of 3 bytes using these commands. The GPIO ports device can be read back from the COMM register using the will not get reset between different STCOMM commands.
- Page 34 LTC6804-1/LTC6804-2 operaTion (SCK) START NACK + STOP SCL (GPIO5) SDA (GPIO4) BLANK NACK SCL (GPIO5) SDA (GPIO4) START SCL (GPIO5) SDA (GPIO4) STOP SCL (GPIO5) SDA (GPIO4) NO TRANSMIT SCL (GPIO5) SDA (GPIO4) 680412 F12 Figure 12. STCOMM Timing Diagram for an I...
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Page 35: Serial Interface Overview
Timing Specifications of I C and SPI master There are two versions of the LTC6804: the LTC6804-1 and the LTC6804-2. The LTC6804-1 is used in a daisy The timing of the LTC6804 I C or SPI master will be chain configuration, and the LTC6804-2 is used in an controlled by the timing of the communication at the addressable bus configuration. -
Page 36: 4-Wire Serial Peripheral Interface (Spi) Physical Layer
LTC6804-1/LTC6804-2 operaTion 4-WIRE SERIAL PERIPHERAL INTERFACE (SPI) 2-WIRE ISOLATED INTERFACE (isoSPI) PHYSICAL PHYSICAL LAYER LAYER The 2-wire interface provides a means to interconnect External Connections LTC6804 devices using simple twisted pair cabling. The – configures serial Port A for Connecting ISOMD to V interface is designed for low packet error rates when the 4-wire SPI. -
Page 37: For More Information
Figure 16 illustrates how the isoSPI circuit operates. A External Connections 2V reference drives the IBIAS pin. External resistors R The LTC6804-1 has 2 serial ports which are called Port B and R create the reference current I . This current sets and Port A. -
Page 38: For More Information
The microprocessor is located on a separate PCB. To achieve 2-wire isolation between the microprocessor PCB = 20 •I = 10mA and the 1st LTC6804-1 PCB, use the LTC6820 support IC. The LTC6820 is functionally equivalent to the diagram in = 2V • •R = 603mV Figure 16. -
Page 39: For More Information
LTC6804-1/LTC6804-2 operaTion • • • • • • • • • • • • • • • • • • • • • • 680412fc For more information www.linear.com/LTC6804-1... -
Page 40: For More Information
• GPIO3 GPIO3 GPIO2 GPIO2 GPIO1 GPIO1 680412 F18a 680412 F18b Figure 18a. Single-Device LTC6804-1 Using 2-Wire Port A Figure 18b. Single-Device LTC6804-2 Using 2-Wire Port A TERMINATED UNUSED PORT ADDRESS = 0×0 LTC6804-1 LTC6804-2 REQUIRED BIAS ICMP IBIAS MISO... -
Page 41: For More Information
Table 23. LTC6804-1 Port A (Slave) isoSPI Port Function LTC6804-1 Operation with Port A Configured for SPI RECEIVED PULSE INTERNAL SPI When the LTC6804-1 is operating with port A as an SPI (PORT A isoSPI) PORT ACTION RETURN PULSE –... - Page 42 Part 3. All this data is read back Figure 20 shows the isoSPI timing diagram for a READ from the SDO port on Part 1 in a daisy-chained fashion. command to daisy-chained LTC6804-1 parts. The ISOMD – pin is tied to V...
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Page 43: For More Information
At minimum, a pair of long isoSPI pulses (–1 and +1) is needed for each device, The LTC6804-1 sends a Long +1 pulse on Port B after it is separated by more than t... -
Page 44: Data Link Layer
LTC6804-1/LTC6804-2 operaTion DATA LINK LAYER 3. Update the 15-bit PEC as follows PEC [14] = IN14, All Data transfers on LTC6804 occur in byte groups. Every byte consists of 8 bits. Bytes are transferred with PEC [13] = PEC [12], the most significant bit (MSB) first. - Page 45 After a broadcast write command to daisy-chained STBR0(P), …, STBR5(P), PEC0(P), PEC1(P), STBR0(S), LTC6804-1 devices, data is sent to each device followed … , STBR5(S), PEC0(S), PEC1(S) by the PEC. For example, when writing the configuration Table 24. PEC Calculation for 0x0001...
- Page 46 This com- command, the SDO line is driven low when the device is mand format can be used with LTC6804-1 and LTC6804-2 busy performing conversions (Figure 23). SDO is pulled parts. See Bus Protocols for Broadcast command format.
- Page 47 LTC6804-1/LTC6804-2 operaTion go high when CSB goes high even if the device has not Bus Protocols completed the conversion. See Programming Examples on Protocol Format: The protocol formats for both broadcast how to use the PLADC command with devices in parallel and address commands are depicted in Table 27 through configuration.
- Page 48 CMD0[6:3]. An addressed device will respond to an address LTC6804-1 and LTC6804-2 Table 27. Broadcast/Address Poll Command CMD0 CMD1 PEC0 PEC1 Poll Data Table 28. Broadcast Write Command (LTC6804-1) CMD0 CMD1 PEC0 PEC1 Data Byte Low … Data Byte High...
- Page 49 LTC6804-1/LTC6804-2 operaTion Table 34. Command Codes COMMAND DESCRIPTION NAME CC[10:0] - COMMAND CODE Write Configuration WRCFG Register Group Read Configuration RDCFG Register Group Read Cell Voltage RDCVA Register Group A Read Cell Voltage RDCVB Register Group B Read Cell Voltage...
- Page 50 LTC6804-1/LTC6804-2 operaTion Table 35. Command Bit Descriptions NAME DESCRIPTION VALUES ADCOPT(CFGR0[0]) = 0 ADCOPT (CFGR0[0]) = 1 27kHz Mode (Fast) 14kHz Mode MD[1:0] ADC Mode 7kHz Mode (Normal) 3kHz Mode 26Hz Mode (Filtered) 2kHz Mode Discharge Permitted Discharge Not Permitted...
- Page 51 LTC6804-1/LTC6804-2 operaTion Table 36. Configuration Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CFGR0 RD/WR GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 REFON SWTRD ADCOPT CFGR1 RD/WR VUV[7] VUV[6] VUV[5]...
- Page 52 LTC6804-1/LTC6804-2 operaTion Table 41. Auxiliary Register Group A REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 AVAR0 G1V[7] G1V[6] G1V[5] G1V[4] G1V[3] G1V[2] G1V[1] G1V[0] AVAR1 G1V[15] G1V[14] G1V[13] G1V[12]...
- Page 53 LTC6804-1/LTC6804-2 operaTion Table 46. Memory Bit Descriptions NAME DESCRIPTION VALUES GPIOx GPIOx Pin Control Write: 0 -> GPIOx Pin Pull-Down ON; 1-> GPIOx Pin Pull-Down OFF (Default) Read: 0 -> GPIOx Pin at Logic 0; 1 -> GPIOx Pin at Logic 1...
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Page 54: Programming Examples
READY The following examples use a configuration of 3 stacked 5. Send commands LTC6804-1 devices: S1, S2, S3. Port A on device S1 is Write Configuration Registers configured in SPI mode (ISOMD pin low). Port A on de- vices S2 and S3 is configured in isoSPI mode (ISOMD pin 1. - Page 55 LTC6804-1/LTC6804-2 operaTion Calculation of serial interface time for sequence above: Clear Cell Voltage Registers 1. Pull CSB low Number of LTC6804-1s in daisy chain stack = n 2. Send CLRCELL command (0x07 0x11) and its PEC Number of bytes in sequence (B):...
- Page 56 LTC6804-1/LTC6804-2 operaTion This example uses a single LTC6804-1 to write a byte 3. Data transmitted to slave during the STCOMM com- of data to an I C EEPROM. The LTC6804 will send three mand is stored in the COMM register. Use the RDCOMM...
- Page 57 3. Data transmitted to slave during the STCOMM com- mand is stored in the COMM register. Use the RDCOMM This example uses a single LTC6804-1 device which has a command to retrieve the data. SPI device connected to it through GPIO3 (CSBM), GPIO4 a.
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Page 58: Simple Linear Regulator
LTC6804-1/LTC6804-2 applicaTions inForMaTion SIMPLE LINEAR REGULATOR IMPROVED REGULATOR POWER EFFICIENCY The LTC6804 draws most of its power from the V input To minimize power consumption within the LTC6804, the pin. 5V ±0.5V should be applied to V . A regulated DC/... -
Page 59: Fully Isolated Power
LTC6804-1/LTC6804-2 applicaTions inForMaTion FULLY ISOLATED POWER current from conducting through internal parasitic paths inside the IC when the isolated power is removed. A simple DC/DC flyback converter can provide isolated power for an LTC6804 from a remote 12V power source READING EXTERNAL TEMPERATURE PROBES as shown in Figure 30. -
Page 60: Expanding The Number Of Auxiliary Measurements
LTC6804-1/LTC6804-2 applicaTions inForMaTion EXPANDING THE NUMBER OF AUXILIARY FILTERING OF CELL AND GPIO INPUTS MEASUREMENTS The LTC6804 uses a delta-sigma ADC, which has delta- The LTC6804 provides five GPIO pins, each of which is sigma modulator followed by a SINC3 finite impulse capable of performing as an ADC input. - Page 61 LTC6804-1/LTC6804-2 applicaTions inForMaTion periodic or higher oversample rates are in use, a differential LTC6804 capacitor filter structure is adequate. In this configuration there are series resistors to each input, but the capacitors connect between the adjacent C pins. However, the dif- ferential capacitor sections interact.
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Page 62: Cell Balancing With Internal Mosfets
LTC6804-1/LTC6804-2 applicaTions inForMaTion CELL BALANCING WITH INTERNAL MOSFETS LTC6804 FILTER C(n) The S1 through S12 pins are used to balance battery cells. If one cell in a series becomes overcharged, an S output can be used to discharge the cell. Each S output has an DISCHARGE internal N-channel MOSFET for discharging. -
Page 63: Power Dissipation And Thermal Shutdown
LTC6804-1/LTC6804-2 applicaTions inForMaTion ADCV command with DCP = 0. In this table, OFF implies The following algorithm could be used in conjunction with Figure 37: that a discharge is forced off during that period even if the corresponding DCC[x] bit is high in the configuration 1. - Page 64 LTC6804-1/LTC6804-2 applicaTions inForMaTion LTC6804 – 680412 F37 Figure 37. Balancing Self Test Circuit 680412fc For more information www.linear.com/LTC6804-1...
- Page 65 LTC6804-1/LTC6804-2 applicaTions inForMaTion /************************************ Copyright 2012 Linear Technology Corp. (LTC) Permission to freely use, copy, modify, and distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies: THIS SOFTWARE IS PROVIDED “AS IS”...
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Page 66: Current Measurement With A Hall Effect Sensor
LTC6804-1/LTC6804-2 applicaTions inForMaTion and produces analog outputs that are connected to GPIO CURRENT MEASUREMENT WITH A HALL EFFECT pins or inputs of the MUX application shown in Figure 32. SENSOR The use of GPIO1 and GPIO2 as the ADC inputs has the... -
Page 67: Using The Ltc6804 With Less Than 12 Cells
LTC6804-1/LTC6804-2 applicaTions inForMaTion USING THE LTC6804 WITH LESS THAN 12 CELLS NEXT HIGHER GROUP OF 8 CELLS If the LTC6804 is powered by the battery stack, the minimum number of cells that can be monitored by the LTC6804 LTC6804 is governed by the supply voltage requirements of the LTC6804. - Page 68 LTC6804-1/LTC6804-2 applicaTions inForMaTion ISOLATION BARRIER (MAY USE ONE OR TWO TRANFORMERS) ISOMD ISOMD • • • • MASTER LTC6804 LTC6804 – – MOSI TWISTED-PAIR CABLE MISO IBIAS IBIAS WITH CHARACTERISTIC IMPEDANCE R ICMP ICMP 680412 F41 Figure 41. isoSPI Circuit...
- Page 69 LTC6804-1/LTC6804-2 applicaTions inForMaTion Implementing a Modular isoSPI Daisy Chain XFMR 100µH CMC The hardware design of a daisy-chain isoSPI bus is identi- • • LTC6804-1 isoSPI LINK cal for each device in the network due to the daisy-chain 10nF point-to-point architecture. The simple design as shown in 10nF Figure 41 is functional, but inadequate for most designs.
- Page 70 LTC6804-1/LTC6804-2 49.9 LTC6804-1 10nF 49.9 GNDD IBIAS ICMP GNDD 49.9 10nF 49.9 GNDD GNDD 10nF* – GNDD 10nF* GNDC 49.9 LTC6804-1 10nF 49.9 GNDC IBIAS ICMP GNDC 49.9 10nF 49.9 GNDC GNDC 10nF* – GNDC 10nF* GNDB 49.9 LTC6804-1 10nF 49.9...
- Page 71 PCB, only a single transformer is required between the diodes are used at each IC to clamp the common mode LTC6804-1 isoSPI ports. The absence of the cable also voltage to stay within the receiver’s input range. The op- reduces the noise levels on the communication lines and tional common mode choke (CMC) provides noise rejection often only a split termination is required.
- Page 72 GNDA 680412 F46 * IF TRANSFORMER BEING USED HAS A CENTER TAP , IT SHOULD BE BYPASSED WITH A 10nF CAP Figure 46. Interfacing an LTC6804-1 with a µC Using an LTC6820 for Isolated SPI Control 680412fc For more information...
- Page 73 LTC6804-1/LTC6804-2 applicaTions inForMaTion LTC6804-2 REGC ISOMD • • IBIAS 1.21k ICMP – GNDC GNDC LTC6804-2 REGB ISOMD • • IBIAS 1.21k ICMP – 100nF 1.21k GNDB LTC6820 GNDB IBIAS MOSI ICMP µC MISO SLOW LTC6804-2 REGA MSTR ISOMD • •...
- Page 74 LTC6804-1/LTC6804-2 applicaTions inForMaTion Table 48. Recommended Transformers TEMPERATURE AEC– MANUFACTURER PART NUMBER RANGE /60s CT CMC (W/LEADS) PINS q200 WORKING HIPOT Dual Transformers Pulse HX1188FNL –40°C to 85°C 60V (est) 1.5kVrms 6.0mm 12.7mm 9.7mm 16SMT – Pulse HX0068ANL –40°C to 85°C 60V (est) 1.5kVrms...
- Page 75 LTC6804-1/LTC6804-2 Interconnecting daisy-chain links between LTC6804-1 Table 49. Recommended Common Mode Chokes devices see <60V stress in typical applications; ordinary MANUFACTURER PART NUMBER pulse and LAN type transformers will suffice. Multi-drop ACT45B-101-2P connections and connections to the LTC6820, in general, Murata...
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Page 76: Package Description
LTC6804-1/LTC6804-2 package DescripTion Please refer to http://www.linear.com/product/LTC6804-1#packaging for the most recent package drawings. G Package 48-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1887 Rev Ø) 12.50 – 13.10* (.492 – .516) 1.25 ±0.12 43 42 41 40 39 38 37 36 35 34 33 31 30 29 28 27 26 25 7.8 –... -
Page 77: Revision History
Section added for isoSPI Layout Guidelines 680412fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- For more information www.linear.com/LTC6804-1 tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. -
Page 78: Typical Application
Up to 92% Charge Transfer Efficiency. 48-Lead Exposed Pad QFN and LQFP Packages 680412fc Linear Technology Corporation LT 1016 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC6804-1 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC6804-1 LINEAR TECHNOLOGY CORPORATION 2013 ● ●...
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