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Vrms Description:
VRMS is the one of the input for PFC Gain Modulator. Besides
it is the input of the Gain Modulator, it also serves for Clean
Digital PFC Brown Out function:
VRMS is used to detect the AC Brown Out (Also, we can call it
Clean Digital PFC brown out.). When VRMS is less than 1.0 V
+/-3%, PFCOUT will be turned off and VEAO will be softly
discharged. When VRMS is greater than 1.75V +/-3%,
PFCOUT is enabled and VEAO is released.
Clean Digital PFC Brown Out
Clean Digital PFC Brown Out provides a clean cut off when
AC input is much lower than regular AC input voltage such as
70Vac.
Inside of Clean Digital PFC Brown Out, there is a
comparator monitors the Vrms (pin 4) voltage. Clean Digital
PFC Brown Out inhibits the PFC, and Veao (PFC error
amplifier output) is pulled down when the Vrms is lower than
off threshold, 1.0V (The off Vin voltage usually corresponds to
70Vac). When the Vrms voltage reaches 1.75V (The On Vin
voltage usually corresponds to 86.6V and when Vin = 80Vac,
Vrms = 1.14V), PFC is on.
Before PFC is turned on, Vrms (pin 4) represents the peak
voltage of the AC input. Before PFC is turned off, Vrms (pin 4)
represents the Vrms voltage of the AC input.
Current Error Amplifier, IEAO
The current error amplifier's output controls the PFC duty
cycle to keep the average current through the boost inductor a
linear function of the line voltage. At the inverting input to the
current error amplifier, the output current of the gain modulator
is summed with a current which results from a negative voltage
being impressed upon the I
I
represents the sum of all currents flowing in the PFC
SENSE
circuit, and is typically derived from a current sense resistor in
series with the negative terminal of the input bridge rectifier.
In higher power applications, two current transformers are
sometimes used, one to monitor the IF of the boost diode. As
stated above, the inverting input of the current error amplifier is
a virtual ground. Given this fact, and the arrangement of the
duty cycle modulator polarities internal to the PFC, an increase
in positive current from the gain modulator will cause the
output stage to increase its duty cycle until the voltage on
I
is adequately negative to cancel this increased current.
SENSE
Similarly, if the gain modulator's output decreases, the output
duty cycle will decrease, to achieve a less negative voltage on
the I
pin.
SENSE
2010/08/03
Rev. 1.2
pin. The negative voltage on
SENSE
Champion Microelectronic Corporation
CM6800T
(Turbo-Speed PFC+Green PWM)
EPA/85+ PFC+PWM COMBO CONTROLLER
Design for High Efficient Power Supply
Cycle-By-Cycle Current Limiter and
Selecting R
SENSE
The I
pin, as well as being a part of the current
SENSE
feedback loop, is a direct input to the cycle-by-cycle current
limiter for the PFC section. Should the input voltage at this pin
ever be more negative than –1V, the output of the PFC will be
disabled until the protection flip-flop is reset by the clock pulse
at the start of the next PFC power cycle.
R
is the sensing resistor of the PFC boost converter. During
S
the steady state, line input current x R
Since the maximum output voltage of the gain modulator is I
max x 7.75K≒ 0.8V during the steady state, R
input current will be limited below 0.8V as well. When VEAO
reaches maximum VEAO which is 6V, Isense can reach 0.8V.
At 100% load, VEAO should be around 4.5V and ISENSE
average peak is 0.6V. It will provide the optimal dynamic
response + tolerance of the components.
Therefore, to choose R
R
+ R
=0.6V x Vinpeak / (2 x Line Input power)
SENSE
Parasitic
For example, if the minimum input voltage is 80VAC, and the
maximum input rms power is 200Watt, R
(0.6V x 80V x 1.414) / (2 x 200) = 0.169 ohm. The designer
needs to consider the parasitic resistance and the margin of
the power supply and dynamic response. Assume R
0.03Ohm, R
= 0.139Ohm.
SENSE
PFC OVP
In the CM6800T, PFC OVP comparator serves to protect the
power circuit from being subjected to excessive voltages if the
load should suddenly change. A resistor divider from the high
voltage DC output of the PFC is fed to VFB. When the voltage
on VFB exceeds ~ 2.75V, the PFC output driver is shut down.
The PWM section will continue to operate. The OVP
comparator has 250mV of hysteresis, and the PFC will not
restart until the voltage at VFB drops below ~ 2.55V. The VFB
power components and the CM6800T are within their safe
operating voltages, but not so low as to interfere with the boost
voltage regulation loop.
The Current Loop Gain (S)
ΔV
ΔD
=
ISENSE
*
ΔD
OFF
V
*
R
OUTDC
≈
S
S
*
L
*
2.5V
Z
: Compensation Net Work for the Current Loop
CI
GM
: Transconductance of IEAO
I
V
: PFC Boost Output Voltage; typical designed value is
OUTDC
380V and we use the worst condition to calculate the Z
R
: The Sensing Resistor of the Boost Converter
SENSE
2.5V: The Amplitude of the PFC Leading Edge Modulation
Ramp(typical)
L: The Boost Inductor
= I
SENSE
, we use the following equation:
SENSE
SENSE
ΔI
EAO
OFF
*
ΔI
ΔI
EAO
SENSE
*
GM
*
Z
CI
I
x 7.75K.
mul
mul
x line
SENSE
+ R
=
Parasitic
=
Parasitic
CI
16
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