Sony MDS-PC3 M-crew Service Manual page 50

• IC151 CXD2662R Digital Signal Processor, Digital Servo Signal Processor (BD BOARD)
Pin No. Pin Name
MNT0 (FOK)
1
MNT1 (SHCK)
2
MNT2 (XBUSY)
3
MNT3 (SLOC)
4
SWDT
5
SCLK
6
XLAT
7
SRDT
8
SENS
9
XRST
10
11 SQSY
DQSY
12
RECP
13
XINT
14
TX
15
OSCI
16
OSCO
17
18 XTSL
DIN0
19
DIN1
20
DOUT
21
DADTI
22
LRCKI
23
XBCKI
24
ADDT
25
DADT
26
27 LRCK
XBCK
28
FS256
29
DVDD
30
A03 to A00
31 to 34
A10
35
A04 to A08
36 to 40
A11
41
DVSS
42
XOE
43
XCAS
44
A09
45
XRAS
46
XWE
47
D1
48
D0
49
D2, D3
50, 51
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
50
I/O
FOK signal output to the system control (monitor output)
O
"H" is output when focus is on
Track jump detection signal output to the system control (monitor output)
O
Monitor 2 output to the system control (monitor output)
O
Monitor 3 output to the system control (monitor output)
O
Writing data signal input from the system control
I
Serial clock signal input from the system control
I (S)
Serial latch signal input from the system control
I (S)
Reading data signal output to the system control
O (3)
Internal status (SENSE) output to the system control
O (3)
Reset signal input from the system control "L": Reset
I (S)
Subcode Q sync (SCOR) output to the system control
O
"L" is output every 13.3 msec. Almost all, "H" is output
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system
O
control
Laser power switching input from the system control "H": Recording, "L": Playback
I
Interrupt status output to the system control
O
Recording data output enable input from the system control
I
System clock input (512Fs=22.5792 MHz)
I
System clock output (512Fs=22.5792 MHz) (Not used)
O
I System clock frequency setting "L": 45.1584 MHz, "H": 22.5792 MHz (Fixed at "H")
Digital audio input (Optical input)
I
Digital audio input (Optical input)
I
Digital audio output (Optical output)
O
Serial data input
I
LR clock input "H" : Lch, "L" : R ch
I
Serial data clock input
I
Data input from the A/D converter
I
Data output to the D/A converter
O
O LR clock output for the A/D and D/A converter (44.1 kHz)
Bit clock output to the A/D and D/A converter (2.8224 MHz)
O
11.2896 MHz clock output (Not used)
O
+3V power supply (Digital)
—
DRAM address output
O
DRAM address output (Not used)
O
DRAM address output
O
DRAM address output (Not used)
O
Ground (Digital)
—
Output enable output for DRAM
O
CAS signal output for DRAM
O
Address output for DRAM
O
RAS signal output for DRAM
O
Write enable signal output for DRAM
O
I/O
Data input/output for DRAM
I/O
I/O
Function