Sony PCV-R532DS Digital Studio Reference Manual page 88

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VAIO Computer Reference Manual
Chip Configuration Sub-Menu
SDRAM Configuration
SDRAM CAS Latency
SDRAM RAS to CAS Delay
SDRAM RAS Precharge Time
SDRAM Cycle Time (Tras, Trc)
SDRAM Address Setup Time
SDRAM Page Closing Policy
CPU Latency Timer
Onboard VGA
Display Cache Paging Mode
Video Memory Cache Mode
Memory Hole At 15M-16M
PCI 2.1 Support
High Priority PCI Mode
Onboard PCI IDE Enable
[By SPD]
User Define
7ns (143MHz)
8ns (125MHz)
[2T]
[2T]
[2T]
[5T, 7T]
6T, 8T
[1T Delay]
No Delay
[All Banks]
One Bank
[Enabled]
Disabled
[Enabled]
Disabled
[Page Open]
Page Close
[UC]
USWC
[Disabled]
Enabled
[Enabled]
Disabled
[Enabled]
Disabled
[Both]
Primary
Secondary
Disabled