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into three zones on 16-word boundaries. The
corresponding bias value is extended to 20 bits (by
appending trailing zeros) and maps the zone into the
20-bit TILINE address space (figure 13).
The three mapping-register sets (each with three
limit registers and three bias registers) are reserved
by system software for specific functions. MAPO is
used by the DXI0 operating system. Interrupts and
XOP codes trap via MAPO. This map also reaches
the TILINE peripheral control space (TPCS). MAP I
is the normal user-task map, and MAP2 is used for
long-distance instructions that provide the user with
access to additional memory space.
The memory-management functions of the DXIO
operating system handle memory allocation and
memory mapping automatically; so mapping is
transparent to most users.
Instruction Set and Addressing Modes
The instruction set of the 990 computer family
readily lends itself to efficient processing through
simple and effective programming (Appendix B). The
990 instructions are divided into nine categories:
arithmetic, logical, shift, compare, branch, load and
move, control and CRU I/O, long distance (990
computer with mapping), and extended operations.
Many of the 990 instructions allow a choice of
one of five addressing modes for one or both of
the operands. The general addressing modes are
(I) workspace-register addressing, (2) workspace-
register indirect addressing, (3) workspace-register
auto-increment addressing, (4) symbolic memory
addressin~,
and (5) indexed memory addressing.
Workspace-register addressing specifies the
workspace register that contains the operand. A
workspace-register address is written as a term with
a value between zero and fifteen and refers to the
sixteen workspace registers identified by the current
workspace pointer.
Workspace-register indirect addressing specifies a
workspace register that contains the address of the
operand. An indirect workspace register address is
written as a term preceded by an asterisk. This form
of addressing allows sequential processing of lists or
arrays without a separate incrementing instruction.
Workspace-register indirect auto-increment
addressing specifies a workspace register that
contains the address of the operand. After the
address is obtained from the workspace register, the
workspace register is incremented. The workspace-
register increment is one for byte operations and two
for word operations.
Symbolic memory addressing specifies the memory
address that contains the operand. An absolute
41
address or a symbolic name contains the operand.
An absolute address or a symbolic name can
be
used as the object of the symbolic address.
Indexed memory addressing specifies a memory
address that contains the desired operand. The
memory address is the sum of the contents of a
workspace (index) register and a symbolic address.
Some 990 instructions imply an addressing mode
other than these five general addressing modes. For
example, all of the immediate instructions use the
next word following the instruction as an immediate
operand. Immediate instructions that require two
operands derive one operand from the next word
and one from a specified workspace register. The
jump instructions use a program-counter relative
addressing mode. The jump instruction includes a
signed displacement value, and the resulting range of
jump is within -128 to
+
127 words of the current
program-counter value. The CR U single-bit I/O
instructions use a displacement value relative to the
contents of current workspace register R12. By
convention, workspace register RI2 contains a CRU
base address, and individual CR U bits are located
relative to that base address.
Extended Operation Instructions.
Extended
operation (XOP) instructions allow the user to
expand the basic 990 instruction set by up to sixteen
additional instructions. The 990 computer allows this
expansion to be an additional logic board or
software subroutines. A bit in the 990 status register
steers XOP execution to the hardware processor (if
present) or to a software XOP vector.
Software XOP vectors are similar to interrupt
vectors, and software XOP processing is similar to
interrupt service. The thirty-two memory-word
locations immediately above the interrupt vectors are
reserved for XOP vectors. Each vector consists of a
workspace pointer and a program count, which are
used for a context switch to one of the XOP
subroutines. The initial workspace pointer, program
count, and status are loaded into the new
workspace; so the initial context can be recovered at
the end of the XOP subroutine. The effective
address of the XOP operand also is loaded into the
new workspace.
The DXIO operating system reserves XOP 15 for
supervisor calls, leaving XOP 0 - XOP 14 available
for user definition. The operating-system generation
program makes specific provision for user definition
of XOP routines. These routines are incorporated
when a DXIO operating system is generated and
installed. The XOP instructions are global; that is,
they can be used by any program that operates
under DXIO control.
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