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Workspace-Pointer (WP)
Register
Memory-Resident
Workspace Registers
Absolute Memory Address
(Hexadecimal)
WP
Can be used f
indexing.
I
or
•
/
RO
WP+OO
R1
WP+02
R2
WP+04
R3
WP+06
R4
WP+08
R5
WP+OA
R6
WP+OC
R7
WP+OE
R8
WP+ 10
R9
WP + 12
R10
WP+ 14
Link or XOP Operand Address
R11
WP+ 16
CRU I/O Base Address
R12
WP+ 18
Stored Workspace Pointer (WP)
R13
WP+ lA
Stored Program Count (PC)
R14
WP+1C
""-
Stored Status (ST)
R15
WP+ 1E
Figure 12. Workspace Pointer and Registers
990 Architecture
The 990 family of computers uses an advanced
memory-to-memory architecture, which offers the
convenience and speed of a register-to-register
architecture without the instruction-overhead
penalties. The 990 processor uses 16-word blocks of
memory as works paces (figure 12). Each memory
location in a workspace is assigned a workspace-
register number and is treated like a 16-bit, general-
purpose hardware register. Any 16-word block in
general memory can be used as a workspace. A
workspace pointer, stored in a hardware register,
locates the currently active workspace. The
workspace concept makes it virtually impossible to
run out of registers; any number of workspaces can
be defined in memory and reached by modifying the
workspace pointer. A dedicated workspace usually is
assigned to each task or subroutine in the program.
A context switch occurs when the program
suspends execution of a task, stores the intermediate
results, executes another task, and usually returns to
the initial task. Interrupt processing, subroutine
calling, and multiple-task interleaving are typical
39
examples of context switches. The workspace
organization of the 990 processor greatly reduces the
instruction and memory-access overhead associated
with a context switch. For example, if the 990
processor used fifteen hardware registers, fifteen store
cycles would
be
required to save all the possible
temporary operands before the context change. By
exchanging the status, program count, and
workspace pointers, the 990 processor can perform a
complete context switch in three store cycles and
two fetch cycles without losing operands or data
from either task. After the context switch, the
hardware workspace-pointer register contains the
memory address of a new workspace; the previous
program count, status, and workspace pointer are
stored in registers 13-15 of the new workspace.
The simplicity of context switching in the 990
processor and the data-handling capability of the
high-speed TILINE data bus make it possible to
efficiently support a large, versatile, multitasking
operating system such as the DXI0 system.
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