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Figure 5-11.
Oscilloscope Block Diagram
5-87.
The horizontal amplifier input is selected between ex
.
functions. Time base Generator or external horizontal in
ternal and mternal scope functions. External
HORIZONTAL POSITION signal from the fr
t
I .
put, are SWitched to a sumatiOn amp where the
.
on pane IS added The result"
DC 11
..
honzontally on the CRT.
·
mg
o set pos111ons the display
5-88.
Six decade sweep ranges from 1
f..l
sec to 100 msec
. . .
.
Generator. Control of the Time base Generator is f
th f
per diVISion are provided by the Time base
rom
e ront panel honzontal switch through the processor.
5-89.
Front panel external horizontal inputs are a
lied
1
.
potentiometer. The wiper of the gain potentiometer i:;h E
0
the top of the honzontal vernier gain
e
XTERNAL HORIZONTAL mput signal to the
5-22
5-65.
Frequency Counter
5-66.
Three possible signal sources are made available to the frequency counter for frequency
determination. Two of the inputs are from internal system points for the determinations of the offset frequency
(OFFSET), and the monitored carrier error frequency (IF/BFO). The third input is the external input (FREQ
CNTR INPUT) on the front panel. A block diagram of the frequency counter function is shown in figure 5-9.
RF SYNTH
REF
FREO
!
A 11
riiiri
PiiliiTTEiii'A-cE _ _ _ _
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PROCESSOR BUS
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PROCESSOR
Figure 5-9.
Frequency Counter Block Diagram
5-67.
The external input signal is routed to the Front Panel Interlace module (A 12). A range Attenuatoron the
Interface module provides variable sensitivity settings according to the vertical range switch setting on the
front panel. An Amplifier following the range Attenuator amplifies and limits the signal amplitude for the
frequency counter input.
5-68.
A Select Switch on the Processor 1/0 module (A7) routes the desired signal to the Frequency Counter
circuitry. The signal selected is controlled by the processor and is determined by the operating mode of the
system.
5-69.
A 16-bit gated accumulator is used to determine the input frequency. Gate times from 1 msec to 10sec
are automatically selected by the processor to give the maximum possible resolution. The gate times are
derived from the RF Synthesizer REFERENCE FREQUENCIES and thus are as accurate as the system time
base.
5-70.
The 16-bit Frequency Counter output is transferred directly to the processor bus through a Peripheral
Interface Adapter (PIA). The processor in turn adjusts the data lor the gate time used and then processes the
information to obtain the required frequency display.
5-71.
Digital Voltmeter (DVM)
5-72. The processor through the DVM circuitry has access to voltage information at a large number of points
throughout the system. From this information the processor is able to determine and display parameters such
as; output power level, modulation level, input power level and the lil<e. In addition an external voltage applied
to the DVM input jack on the front panel can oe measured and displayed lor external voltage measurements. A
block diagram of the DVM function is shown in figure 5-10.
5-19
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