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A3
Bl-2315
81-2376
---Aa
BRACKET AS
SHOWN ON
MODELS VOOJ
AND V004 ONLY
Figure 5·1.
Communications System Analyzer, Top View, Cover Removed
Figure 5·2.
Communications System Analyzer. Bottom View, Cover Removed
5-6
4215-12
•
5-16.
THEORY OF OPERATION
5-17.
General
5-18.
The operation of the Communications System Analyzer can be divided into nine basic functions;
Generate, Power Meter, Monitor. Duplex Generator, Code Synthesizer, Frequency Counter, Digital Voltmeter
(DVM). Oscilloscope, and Sinad Meter. The general operation of the unit will simultaneously incorporate the
basic functions to provide the total capability of the system.
5-19.
The following discussion will cover the block diagrams for each of the basic functions plus a discussion
on the processor control of the system. A functional block diagram of the total system is shown in figure 5-3.
Only the major signal paths between each of the modules are shown to clarify the total system configuration.
5-20.
System Control
5·21.
System Control is the primary responsibility of the internal microprocessor. Front panel control and
system status inputs to the processor are manipulated by the processor to provide the control for the operating
mode. From the front panel the processor monitors the keyboards, the function select switch, the modulation
control switch. the RF scan switch, the image switch, the bandwidth switch, the horizontal and vertical range
switches. and the step attenuator switch. This information plus internal status information causes the
processor to display the appropriate information on the CRT to program the center frequency, to set up the
generate or monitor mode, and to make the internal switching arrangements lor the selected operating state.
5·22.
The interlace to and !rom the microprocessor is via the processor bus. This bus consists of a 16-bit
address bus. an 8-bit data bus. and a 7-bit control bus. This bus interfaces the processor to its program
memory (ROM). scratch pad memory (RAM), IEEE interface, and the peripheral interface adapters (PIA). The
PIA is the mechanism by which the processor interfaces with the system. A PIA consits of a dual 8-bit latch
which may be programmed as either an input or output for the microprocessor. System input and control
information passes to and from the microprocessor via three system control buses attached to a PIA.
5-23.
Each system control bus consists of a 4 bit address bus. a 4 bit data bus, and an enable line. The 4
address bits determine which of 16 possible latches the 4 bits of data is to be sent to or received from. The
enable line triggers the actual transfer of data. The three control buses within the system are called the RF
control bus and the AF control buses 1 and 2. The RF control bus is as described above while the AF control
buses consist of a single 4-bit address and 4-bit data bus and two enable lines. The resulting total input/output
capability for the system buses is 16latches at 4-bits each times 3 buses or 192 bits. A tabulation of buses and
the controlling or input function of each bit is shown in table 5·2.
5-24.
Systems with the IEEE remote control option interface the IEEE bus to the processor bus through a
general purpose interface bus adapter (GPIB) on the IEEE interface module. When enabled all control inputs
to the system pass through the IEEE bus and front panel controls are ignored. For more information on IEEE
control see section 21.
5·25.
Generate Mode
5-26.
The generate mode provides a variable level RF output that is phase locked to the internal 10 MHz
standard. AM, FM. and Sideband Modulation are possible on the output signal. A block diagram of the
generate mode is shown in figure 5·4.
5· 7 /( 5-8 blank)
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