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Flag Over Error flag. 0 means error number has not been
confirmed. The bit will set to 1 when more than 4 symbols
10 RSM4
RS_ECC errors are detected and have not been corrected in the
current codeword.
WithError_Flag. This bit will set to 1 when RS_ECC any errors are
9
RSER
detected in the current codeword, writing 1 to this bit will clear it.
ECC Encode or Decode Ready flag.
If RS ECC selected, the bit will set to 1 when the RS encode or
decode engine works on 9-bit symbols has completed. Hardware
8
ERDY
automatically reset to 0 when the next sector DMA starts.
If selected Hamming ECC. This bit will set to 1 when the HM
encode or decode engine works has completed, Hardware
automatically reset to 0 when the next sector DMA start.
When main and spare sectors are all 0xFF, ECC does not report
error.
7
EAFE
0: Disable
1: Enable
6:5
-
Reserved.
Encoding mode selection of User Data in RS － ECC
4
0: User Data encodes
ECCM
1: User Data does not encode
3
--
Reserved
User HM ECC Control.
2
UHEC
0: normal
1: user
ECC TYPE SEL.
Bit
ECC Type Select
0 0 disable Hamming Code ECC & Read Solomon Code ECC.
1:0 TYPE
0 1 enable Hamming Code ECC, disable Read Solomon Code ECC.
1 0 enable Read Solomon Code ECC, disable Hamming Code ECC.
1 1 reserved.
14.2.14
Hamming ECC Register0
Offset= 0x0034
Copyright
©
Ver 1.1
NAND_HAMECC0
Table 130: NAND_HAMECC0 Bit Field Description
Actions Semiconductor Co., Ltd. 2006. All rights reserved.
Page 123
ATJ2135 PROGRAMMING GUIDE
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