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Actions ATJ2135 Product

Programming Guide

Latest Version: 1.1

Jan 2007

Table of Contents

Summary of Contents for Actions ATJ2135

Page 1 Actions ATJ2135 Product Programming Guide Latest Version: 1.1 Jan 2007...
Page 2: Declaration
Actions’ products. The information presented in this document does not form part of any quotation or contract of sale. Actions assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Actions’...
Page 3 ATJ2135 PROGRAMMING GUIDE injury or severe property damage. Any and all such uses without prior written approval of an Officer of Actions and further testing and/or modification will be fully at the risk of the customer. Copies of this document and/or other Actions product literature, as well as the Terms and Conditions of Sale Agreement, may be obtained by visiting Actions’...
Page 4: Table Of Contents
CMU_BUSCLK ......................38 4.2.5 CMU_SDRCLK......................39 4.2.6 CMU_NANDCLK......................39 4.2.7 CMU_SDCLK .......................40 4.2.8 CMU_UARTxCLK ......................40 4.2.9 CMU_MHACLK ......................41 4.2.10 CMU_DMACLK ......................41 4.2.11 CMU_FMCLK .......................42 4.2.12 CMU_MCACLK ......................43 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 3 2007-1-29...
Page 5 SRSCtl Register (CP0 Register 12, Select 2)............70 7.2.3 SRSMap Register (CP0 Register 12, Select 3)............71 7.2.4 Processor Identification (CP0 Register 15, Select 0)........... 71 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 4 2007-1-29...
Page 6 Description........................87 10.2 Register List........................87 10.2.1 DMA_CTL........................88 10.2.2 DMA_IRQEN........................88 10.2.3 DMA_IRQPD .......................90 10.2.4 DMA_MODEx ......................91 10.2.5 DMA_SRCx........................93 10.2.6 DMA_DSTx ........................93 10.2.7 DMA_CNTx ........................94 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 5 2007-1-29...
Page 7 Register List and Memory Map .................108 13.2.1 MCA_CTL ........................109 NAND FLASH Interface .................. 111 14.1 Description........................111 14.2 Register List........................111 14.2.1 NAND_CTL........................ 112 14.2.2 NAND_STATUS......................114 14.2.3 NAND_FIFOTIM......................115 14.2.4 NAND_CLKCTL......................116 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 6 2007-1-29...
Page 8 SD_CMD ........................136 15.2.6 SD_ARG........................137 15.2.7 SD_CRC7........................137 15.2.8 SD_RSPBUF0 ......................137 15.2.9 SD_RSPBUF1 ......................137 15.2.10 SD_RSPBUF2 .......................138 15.2.11 SD_RSPBUF3 .......................138 15.2.12 SD_RSPBUF4 .......................138 15.2.13 SD_DAT........................138 15.2.14 SD_CLK .........................139 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 7 2007-1-29...
Page 9 UART2_STAT ......................155 IR Interface...................... 157 20.1 Description........................157 20.2 Register List........................157 20.2.1 IR_PL .........................158 20.2.2 IR_RBC ........................158 Key Scan ......................159 21.1 Description........................159 21.2 Register List........................162 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 8 2007-1-29...
Page 10 23.2.5 DAC_Analog......................178 ADC........................181 24.1 Description........................181 24.2 Register List........................181 24.2.1 ADC_CTL........................181 24.2.2 ADC_FIFOCTL......................183 24.2.3 ADC_DAT ........................184 24.2.4 ADC_Analog......................185 24.2.5 ADC_Debug ......................186 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 9 2007-1-29...
Page 11 ATJ2135 PROGRAMMING GUIDE Appendix ......................188 25.1 Acronym and Abbreviations ..................188 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 10 2007-1-29...
Page 12: List Of Figures
ATJ2135 PROGRAMMING GUIDE List of Figures Figure 1: ATJ2135 Functional Block Diagram ..............28 Figure 2: ATJ2135 Clock Diagram..................32 Figure 3: CMU Framework.....................33 Figure 4: SPECIAL CLK Framework ..................34 Figure 5: Watch Dog/RTC/Timers Block Diagram..............47 Figure 6: Performance Counters Block Diagram ..............75 Figure 7: How to Use MHA in a System................101...
Page 13: List Of Tables
ATJ2135 PROGRAMMING GUIDE List of Tables Table 1: ATJ2135 Pin Definition ...................21 Table 2: ATJ2135 Physical Memory Map ................29 Table 3: CMU Base Address ....................35 Table 4: HOSC/CMU Register Address .................35 Table 5: CMU_COREPLL Bit Field Description ..............35 Table 6: CMU_DSPPLL Bit Field Description................36 Table 7: CMU_AUDIOPLL Bit Field Description ..............37...
Page 14 Table 71: SRAMOC_CTL Bit Field Description ..............85 Table 72: SRAMOC_STAT Bit Field Description ..............86 Table 73: DMA Base Address ....................87 Table 74: Bus Controller and DMA Control Register Address..........87 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 13 2007-1-29...
Page 15 Table 111: MCA IO Registers ....................108 Table 112: MCA Memory.....................108 Table 113: MCA_CTL Bit Field Description ................109 Table 114: NAND FLASH Block Base Address..............111 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 14 2007-1-29...
Page 16 Table 151: SD_CRC7 Bit Field Description ................137 Table 152: SD_RSPBUF0 Bit Field Description ..............137 Table 153: SD_RSPBUF1 Bit Field Description ..............137 Table 154: SD_RSPBUF2 Bit Field Description ..............138 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 15 2007-1-29...
Page 17 Table 191: GPIO Registers Block Base Address..............166 Table 192: GPIO Registers Offset Address ................166 Table 193: GPIO_AOUTEN Bit Field Description..............166 Table 194: GPIO_AINEN Bit Field Description ..............166 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 16 2007-1-29...
Page 18 Table 212: ADC_FIFOCTL Bit Field Description ..............183 Table 213: ADC_DAT Bit Field Description.................185 Table 214: ADC_Analog Bit Field Description ..............185 Table 215: ADC_Debug Bit Field Description ..............186 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 17 2007-1-29...
Page 19: Revision History
ATJ2135 PROGRAMMING GUIDE Revision History Date Revision Description Author Dec 2006 Initial release; Fionawx Updated based on SD Spec 0.40M Jan 2007 Fionawx (061124) Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 18 2007-1-29...
Page 20: Introduction
8k to 96k. The built-in audio codec is able to switch inputs within headphones, microphones, FM radios and direct drive for low impedance earphones. The ATJ2135 also provides integrated SDRAM and Flash interfaces; IIC, IR and UART etc. interfaces for changeable control and transfer modes. The ATJ2135 therefore provides a true “ALL-IN-ONE”...
Page 22: Pin Definition
SDRAM Interface Data 0 SDRAM_A0 SDRAM Interface Address 0 SDRAM_A1 SDRAM Interface Address 1 SDRAM_DQ1 SDRAM Interface Data 1 SDRAM_A2 SDRAM Interface Address2 SDRAM_A3 SDRAM Interface Address 3 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 21 2007-1-29...
Page 23 SDRAM Interface Data 8 SDRAM_A12 SDRAM Interface Address12 GPIOA26 GPIOA Port 26 SDRAM_DQ9 SDRAM Interface Data 9 SDRAM_DQ10 SDRAM Interface Data10 SDRAM_DQ11 SDRAM Interface Data11 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 22 2007-1-29...
Page 24 VBUS VBUS UVCC UVCC Data Plus Minus UGND UGND RREF Reference Resistance AGNDP AGND AVDDP AVDD UGNDS UGND UVCCS UVCC MICINL Microphone In Left Channel Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 23 2007-1-29...
Page 25 KS_IN[0] KEY Scan in 0 GPIOA8 GPIOA Port 8 KS_OUT[0] Key Scan Output 0 GPIOA12 GPIOA Port12 NF_CEB3 NAND FLASH Interface CE3 RESETB System RESET Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 24 2007-1-29...
Page 26 SD CARD Interface CLOCK 16mA /CE6 LCD Interface CE6 GPIOB29 GPIOB Port 29 NF_ALE NAND FLASH ALE /RGB_WD[0] RGB Interface Data0 GPIOA0 GPIOA Port 0 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 25 2007-1-29...
Page 27 RGB Interface Data 6 /SD_DAT[5] SD card Interface Data 5 NF_D[14] NAND FLASH Interface Data 14 /RGB_WD[7] RGB Interface Data 7 /SD_DAT[6] SD card Interface Data 6 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 26 2007-1-29...
Page 28 1 PWR----Power Supply 2 AI-----Analog Input 3 AO----Analog Output 4 O----Output 5 I----Input 6 BI----Bi-direction 7 USCU, USCL----Schmitt Type 8 OD----Open Drain 9 ABI----Analog Bi-derection Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 27 2007-1-29...
Page 29: Functional Block And Memory Map
Mem/IO Mem/IO 53M@8 USB 2.0 Arbitor Bridge Key scan Interrupt Control LR ADC IIC(2) I/F DAC+PA IrDa I/F GPIO Figure 1: ATJ2135 Functional Block Diagram Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 28 2007-1-29...
Page 30: Memory Map
SDRAM Controller 0x10080000 0x1008FFFF 0x10090000 0x1009FFFF Reserved 0x100A0000 0x100AFFFF FLASH I/F 0x100B0000 0x100BFFFF SD IF 0x100C0000 0x100CFFFF 0x100D0000 0x100DFFFF Reserved 0x100E0000 0x100EFFFF 0x100F0000 0x100FFFFF YVU2RGB Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 29 2007-1-29...
Page 31 Reserved 0x19000000 0x19FFFFFF Reserved 0x1A000000 0x1AFFFFFF Reserved 0x1B000000 0x1BFFFFFF Reserved 0x1C000000 0x1CFFFFFF CE3 (LCD) 0x1D000000 0x1DFFFFFF CE2 (LAN) 0x1E000000 0x1EFFFFFF Reserved 0x1F000000 0x1FFFFFFF CE0 (BROM) Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 30 2007-1-29...
Page 32: Clock Management Unit (Cmu)
Two 24bit timers are integrated in this IC. User may select either low or high oscillator as the source. 4.1 CMU/HOSC Description ATJ2135 system is mainly driven mainly by 4 clocks. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved.
Page 33: Figure 2: Atj2135 Clock Diagram
The four main clocks and a special clock for module are managed by CMU. The CMU framework is as follows. Core_Clk is used only in CMU module. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 32 2007-1-29...
Page 34: Figure 3: Cmu Framework
Clock Generator CMU Framework Figure 3: CMU Framework The DMA special channel clock configuration is in DMA blocks. The SPECIAL CLK framework is as follows: Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 33 2007-1-29...
Page 35: Figure 4: Special Clk Framework
/DIV[3:0] SD_CL CORE_CL /DIV[3:0] 1/128 MHA_C CORE_CLK /DIV[3:0] MCA_C CORE_CLK /DIV[3:0] LOSC RTC_C _CLK Key_CL The divider can be reused Figure 4: SPECIAL CLK Framework Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 34 2007-1-29...
Page 36: Cmu/Hosc Register List
CMU_DEVRST 0x0084 Device Reset Control Register 4.2.1 CMU_COREPLL Core PLL Control Register Offset=0x0000 Table 5: CMU_COREPLL Bit Field Description Name Description R/W Reset Reserved 31:11 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 35 2007-1-29...
Page 37: Cmu_Dsppll
Formula: 6M* DPCK, Range:12~378M, 5:0 DSPPLLCLK Definition: 6M If DPCK is less than 0x02, the DSP PLL will be unstable. 4.2.3 CMU_AUDIOPLL Audio PLL Control Register Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 36 2007-1-29...
Page 38: Table 7: Cmu_Audiopll Bit Field Description
111: useless Note: AUDIOPLLCLK maps to DSP port 3FEE DAC_FREQ_SELECT, and ADC_FREQ_SELECT field. When operating one of these fields, the other field will be changed. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 37 2007-1-29...
Page 39: Cmu_Busclk
Div 2~16 0: /2 PCLKDIV 1: /2 11..8 2: /3 …… 15: /16 CPU Clock Selection 00: 32.768k 01: 24M 7..6 CORECLKS 10: Core_Clk 11: reserved Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 38 2007-1-29...
Page 40: Cmu_Sdrclk
Table 9: CMU_SDRCLK Bit Field Description Name Description Reset 31:2 Reserved SDRDIV SDRAM Clock Divisor /1 (default) 4.2.6 CMU_NANDCLK NAND Interface CLK Control Register Offset=0x0018 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 39 2007-1-29...
Page 41: Cmu_Sdclk
0: Disable Div 128 SD Interface Clock Divisor 0: /1 1: /2 SDDIV 2: /3 …… 15: /16 4.2.8 CMU_UARTxCLK Uart2 CLK Control Register Offset=0x002C Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 40 2007-1-29...
Page 42: Cmu_Mhaclk
DMA CLK Control Register Offset=0x0030 Table 14: CMU_DMACLK Bit Field Description Name Description Reset 31:4 Reserved DMA 7 (Special Channel) Clock Enable D7EN 1: Enable 0: Disable Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 41 2007-1-29...
Page 43: Cmu_Fmclk
FM Clock Output Selection CLKS 0: 32.768k 1: 24M FM Clock Output Enable (From Test Pin) OUTE 1: Enable test pin output Clock 0: Disable test pin output Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 42 2007-1-29...
Page 44: Cmu_Mcaclk
Switch APB clock. Reserved IIC control register clock enable. Switch APB clock. UART control register clock enable. UART Switch APB clock and UART special clock. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 43 2007-1-29...
Page 45 Switch AHB clock. YUV2RGB block clock enable. Switch AHB clock. Reserved NOTE: Some other clocks are always on, include: APB_En (APB bridge clock), PMU_En, CMU_En, RTC_En, INTC_En. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 44 2007-1-29...
Page 46: Cmu_Devrst
DMA control block Reset PCNT RISC Performance Count block clock Reset Reserved SDRAM Control register and SDRAM block Reset Note: Write ‘0’ to reset the block Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 45 2007-1-29...
Page 47: Rtc/Losc/Watch Dog/Timers Block Description
ATJ2135 PROGRAMMING GUIDE 4.3 RTC/LOSC/Watch Dog/timers Block Description ATJ2135 has a low frequency oscillator, which can choose a built-in source or an external one. Meanwhile the chip also has RTC (Real Time Clock) with alarm IRQ. The alarm IRQ can wake up the system. For this purpose, the chip also has the watch dog circuit.
Page 48: Rtc/Losc/Watch Dog Register List
Timer1 Timer1_Load Figure 5: Watch Dog/RTC/Timers Block Diagram 4.4 RTC/LOSC/Watch Dog Register List Table 19: RTC Base Address Name Physical Base Address KSEG1 Base Address Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 47 2007-1-29...
Page 49: Rtc_Ctl
Switch RTC clock to 32k, and output divided clock to pad. VERI 1: Enable 0: Disable RTC Leap Year bit LEAP 1: leap year 0: non leap year Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 48 2007-1-29...
Page 50: Rtc_Dhms
Table 22: RTC_DHMS Bit Field Description Description Name Reset Binary code Reserved 31:27 01H-07H 26:24 Reserved 23:21 HOUR 00H-17H 20:16 Reserved 15:14 00H-3BH 13:8 Reserved Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 49 2007-1-29...
Page 51: Rtc_Ymd
RTC Day Hour Minute and Second Alarm Register Offset=0x000C Table 24: RTC_DHMSALM Bit Field Description Description Name Reset Binary code Reserved 31:21 00H-17H 20:16 HOURAL Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 50 2007-1-29...
Page 52: Rtc_Ymdalm
0: disable To verify watch dog clock in normal mode. Reserved IRQP Watch dog IRQ pending bit, writing 1 to this bit will clear it Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 51 2007-1-29...
Page 53: Rtc_T0Ctl
When this bit is enabled, TIMER0_Zero_IRQ sent out the IRQ signal RW 0 until the pending bit was cleared. Timer0 IRQ Pending, ZIPD RW 0 Writing 1 to clear this bit. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 52 2007-1-29...
Page 54: Rtc_T0
Writing 1 to clear this bit. Note: The Count can only count down. When count becomes zero, IRQ will be sent. 4.4.10 RTC_T1 RTC Timer1 Value Offset=0x0024 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 53 2007-1-29...
Page 55: Table 30: Rtc_T1 Bit Field Description
ATJ2135 PROGRAMMING GUIDE Table 30: RTC_T1 Bit Field Description Name Description Reset 31:24 Reserved 23:0 Read or write current Timer1 value Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 54 2007-1-29...
Page 56: Interrupt Controller
High Level PC (Performance Counter) High Level 2Hz/WatchDog High Level TIMER1 High Level TIMER0 High Level High Level High Level High Level External High Level Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 55 2007-1-29...
Page 57: Interrupt Controller Register List
INTC_CFG1 0x000C Interrupt Config register 1 INTC_CFG2 0x0010 Interrupt Config register 2 INTC_EXTCTL 0x0014 External Interrupt control and status register 5.2.1 INTC_PD Interrupt Pending Register. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 56 2007-1-29...
Page 58: Intc_Msk
IIC2 Interrupt Mask Bit Reserved Reserved External IRQ Interface Interrupt Mask Bit KEY Interrupt Mask Bit DMA Interrupt Mask Bit RTC Interrupt Mask Bit T0 Interrupt Mask Bit Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 57 2007-1-29...
Page 59: Intc_Cfgx
NAND Interface Interrupt CFGx Bit Reserved DAC Interrupt CFGx Bit ADC Interrupt CFGx Bit Reserved Reserved IIC1 IIC1 Interrupt CFGx Bit IIC2 IIC2 Interrupt CFGx Bit Reserved Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 58 2007-1-29...
Page 60: Intc_Extctl
00 High level active. 26:25 E1TYPE 01 Low level active. 10 rising edge-triggered. 11 Falling edge-triggered. Enable External interrupt 1 E1EN 0 Disable 1 Enable 23:17 Reserved Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 59 2007-1-29...
Page 61 E0PD Write 1 to the bit will clear it. If external interrupt source 0 is edge-triggered, this bit must be cleared by software after detected. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 60 2007-1-29...
Page 62: Pmu/Dc-Dc Converter
External power PIN: VCCOUT PMU Working Mode Li+ Battery, 2 Inductors Li+ Battery, 1 Inductor for VCC Li+ Battery, 1 Inductor for VDD Li+ Battery, No Inductor Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 61 2007-1-29...
Page 63: Register List
30..28 VCVS 3.0V 2.9V 2.8V 2.7V 2.6V Low Battery Non-masked Interrupt Mask bit LBNM LBNMI_ mask, “1”, OPEN VDD Voltage Set Register 26..24 VDVS[3:1] 2.0V Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 62 2007-1-29...
Page 64 1: Enable, 0: Disable VCCOUT Enable VCOE 1: Enable 0: Disable LRADC 6bit Enable LA6E 1: Enable 0: Disable LRADC 4bit Enable LA4E 1: Enable Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 63 2007-1-29...
Page 65: Pmu_Lradc
VDV0 1: +50mV for VDD Power Mode PWRM 1*----Li+ 6.3.2 PMU_LRADC Low Resolution ADC Data Register Offset=0x0004 Table 43: Low Resolution ADC Data Register Description Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 64 2007-1-29...
Page 66: Pmu_Chg
101*: 300mA 110: 400mA 111: 500mA Charging Status. STAT 0: not charging, 1: charging. Charging phase 00: Reserved 26-25 CHGPHASE 01: Pre-charging 10: Constant current Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 65 2007-1-29...
Page 67 Temperature Monitor’s Maxim Temperature Setting: TMPSET 45C * Low Battery Non-mask Interrupt Voltage Setting 00* 2.9V LBNMIVS 3.1V 3.3V 3.5V Low Battery Reset Voltage setting LBRVS 2.7V 2.9V Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 66 2007-1-29...
Page 69: 32-Bit Risc Core
ATJ2135 PROGRAMMING GUIDE 32-BIT RISC Core The core follows MIPS 4KEc SPEC. This Chapter describes the features of RISC Core which are not implemented or different from MIPS 4KEc SPEC. 7.1 Coprocessor 0 Description In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation and cache protocols, the exception control system, the processor’s diagnostics...
Page 70: Intctl Register (Cp0 Register 12, Select1)
Note 2: Registers used in debug. Note 3: Registers used in memory management. 7.2.1 IntCtl Register (CP0 Register 12, Select1) IntCtl register controls the expanded interrupt capability. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 69 2007-1-29...
Page 71: Srsctl Register (Cp0 Register 12, Select 2)
Table 48: SRSCtl Bit Field Description Name Description Reset 31:30 Must be written as zeros; returns zero on read. 29:26 This field is always 0 to indicate that only the Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 70 2007-1-29...
Page 72: Srsmap Register (Cp0 Register 12, Select 3)
Revision of the processor and reset on each new major revision. Patch Level If a patch is made to modify an older revision of the Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 71 2007-1-29...
Page 73: Ebase Register (Cp0 Register 15, Select 1)
Must be written as 0. Returns zero on reads. This field is always 10 to indicate merging is enabled in the 18:17 32 bytes collapsing write buffer. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 72 2007-1-29...
Page 74: Config1 Register (Cp0 Register 16, Select1)
This field is always 0 to indicate the core not contains Performance Counters. This bit is always 1 to indicate that one or more Watch Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 73 2007-1-29...
Page 75: Config2 Register (Cp0 Register 16, Select2)
This bit will always be 0 to indicate SmartMIPS is not presented. This bit is always 0 to indicate trace logic is not implemented. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 74 2007-1-29...
Page 76: Performance Counters Description
Table 57: Performance Counters Registers Offset Register Name Description 0x0000 PCNT_CTL Performance Counters Control register 0x0004 PCNT_PC0 Performance Counter 0 register 0x0008 PCNT_PC1 Performance Counter 1 register Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 75 2007-1-29...
Page 77: Pcnt_Ctl
EXL1 0 Disable counter 1 while EXL = 1. 1 Enable counter 1 while EXL = 1. Enable counter 1. C1EN 0 Disable counter 1. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 76 2007-1-29...
Page 78: Pcnt_Pcx
C0EN 0 Disable counter 0. 1 Enable counter 0. 7.4.2 PCNT_PCx Performance Counter register0, Offset=0x0004. Performance Counter register1, Offset=0x0008 Table 59: PCNT_PCx Bit Field Description Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 77 2007-1-29...
Page 79: Other Reference
Undefined request of counter 0 and counter 1 is ORed together. 7.5 Other Reference Please refer to MIPS32. 4KEc. Processor Core Datasheet MD00111-2B-4KEC-DTS-02.00.pdf Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 78 2007-1-29...
Page 80: Sdram Interface
ATJ2135 PROGRAMMING GUIDE SDRAM Interface 8.1 SDRAM Interface Description SDRAM interface can support both SDRAM (Synchronous DRAM) and Mobile SDRAM. It has the following features: Supports SDRAM and Mobile SDRAM Separate I/O power supply supporting 1.8V, 2.5V and 3.3V Supports 3.3V SDRAM of clock frequency up to PC100 Supports 3.3V SDRAM of capacity up to 512Mbits...
Page 81: Sdr_Ctl
Priority Special DMA, "0" is the highest: 14:12 PRIO 0: BUS>DMA4>DMA5>DMA6>DMA7 1: MA4>BUS>DMA5>DMA6>DMA7 2: MA4>DMA5>BUS>DMA6>DMA7 3: MA4>DMA5>DMA6>BUS>DMA7 4~7: MA4>DMA5>DMA6>DMA7>BUS SDRAM Bus width BUSW 8bit 16bit Reserved Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 80 2007-1-29...
Page 82: Sdr_En
Table 63: SDR_EN Bit Field Description Name Description Reset 31:1 Reserved － SDRAM Enable: Disable Enable 8.2.3 SDR_CMD SDRAM Command Register Offset=0x0010 Table 64: SDR_CMD Bit Field Description Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 81 2007-1-29...
Page 83: Sdr_Stat
SDRAM Status Register Offset=0x0014 Table 65: SDR_STAT Bit Field Description Name Description Reset 31:1 Reserved － Initiation Completed Flag, not completed completed Write 1 to clear it. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 82 2007-1-29...
Page 84: Sdr_Autorfc
0 1 0 0 1 1 Others reserved. Burst Type A3 Burst Type 0 Sequential 1 Interleave Burst Length A2 A1 A0 BL 0 0 0 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 83 2007-1-29...
Page 85: Sdr_Mobile
1 0 1 One-eighth array (BA1 = BA0 = Row Address MSB = 0) 1 1 0 One-sixteenth array (BA1 = BA0 = Row Address MSB = 0) 1 1 1 Reserved Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 84 2007-1-29...
Page 86: Sram On Chip
ATJ2135 PROGRAMMING GUIDE SRAM on Chip 9.1 Description ATJ2135 has 96k-Byte SRAM which can map 24k*32bit (for MIPS) or 32k*24bit (for DSP). It can be operated in byte. 9.2 Register List Table 69: SRAMOC Base Address Name Physical Base Address KSEG1 Base Address...
Page 87: Sramoc_Stat
Table 72: SRAMOC_STAT Bit Field Description Name Description R/W Reset 31:27 Reserved Reserved Reserved Reserved 23:20 Current program number 19:16 Final program number 15:0 Final address Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 86 2007-1-29...
Page 88: Dma/Bus Arbiter
ATJ2135 PROGRAMMING GUIDE DMA/Bus Arbiter 10.1 Description ATJ2135 DMA controller contains 8 tasks, which are divided into two types, bus DMA and special channel DMA. System bus adopts the subset of AMBA bus protocol. 10.2 Register List Table 73: DMA Base Address...
Page 89: Dma_Ctl
0: CPU>DMA0>DMA1>DMA2>DMA3 CPUPRIO RW 0 1: DMA0>CPU>DMA1>DMA2>DMA3 2: DMA0>DMA1>CPU>DMA2>DMA3 3: DMA0>DMA1>DMA2>CPU>DMA3 4~15: DMA0>DMA1 >DMA2>DMA3>CPU 10.2.2 DMA_IRQEN DMA IRQ Enable Offset=0x0004 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 88 2007-1-29...
Page 90: Table 78: Dma_Irqen Bit Field Description
IRQ Enable. DMA1 Half-transfer Complete D1HE IRQ Enable. DMA1 Transfer Complete D1TE IRQ Enable. DMA0 Half-transfer Complete D0HE IRQ Enable. DMA0 Transfer Complete D0TE IRQ Enable. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 89 2007-1-29...
Page 91: Dma_Irqpd
IRQ Pending. DMA2 Transfer Complete D2TP IRQ Pending. DMA1 Half-transfer Complete D1HP IRQ Pending. DMA1 Transfer Complete D1TP IRQ Pending. DMA0 Half-transfer Complete D0HP IRQ Pending. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 90 2007-1-29...
Page 92: Dma_Modex
Valuable when DST_Fix=0 . If DST_Burst_Len is burst 4or8, DST_Dir must increase. Destination Fix Address(IO) or Not; DFXA RW 0 0: Not fixed, 1: Fix Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 91 2007-1-29...
Page 93 SRC_Colloum_Mode must be 0. Reserved Source DSP Mode 1: enable DSP mode SDSP RW 0 0: disable DSP mode Valuable when SRC_Collum_Mode =0 and SRC_Tran_Wide=0, SRC_Burst_Len=0, SRC_Fix=0. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 92 2007-1-29...
Page 94: Dma_Srcx
SRC_Tran_Wide. 10.2.5 DMA_SRCx DMAx SRC Register Offset=0x0104+x*0x0020 Table 81: DMA_SRCx Bit Field Description Name Description Reset 31:0 DMA Source Address 10.2.6 DMA_DSTx DMAx DST Register Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 93 2007-1-29...
Page 95: Dma_Cntx
Description Reset 31:20 Reserved 19:0 REMAIN DMA Remain Byte 10.2.9 DMA_CMDx DMAx CMD Register Offset=0x0114+x*0x0020 Table 85: DMA_CMDx Bit Field Description Name Description R/W Reset Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 94 2007-1-29...
Page 96 After TC the bit will be cleared. The low-go-high edge of this STAR bit will load SRC start address, DST start address, byte count into current working counters. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 95 2007-1-29...
Page 97: 24-Bit Dsp Core
ATJ2135 PROGRAMMING GUIDE 24-BIT DSP Core 11.1 Description DSP Core has the following features: Read ADC data directly Write some DAC/ADC control register With Byte selection function 24bit instruction and data bus 1 instruction per machine cycle Maximum 96 (=12x8) Million Instructions Per Second (MIPS) and extra mass...
Page 98: Dsp_Hdr0
Offset=0x0004 Table 89: DSP_HDR1 Bit Field Description Name Description Reset 31:8 Reserved HDR1 HIP DATA Register 1 [7:0] 11.2.3 DSP_HDR2 DSP HIP Data Register2 Offset=0x0008 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 97 2007-1-29...
Page 99: Dsp_Hdr3
HIP DATA Register 4 [7:0] 11.2.6 DSP_HDR5 DSP HIP Data Register5 Offset=0x0014 Table 93: DSP_HDR5 Bit Field Description Name Description Reset 31:8 Reserved HDR5 HIP DATA Register 5 [7:0] Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 98 2007-1-29...
Page 100: Dsp_Hsr6
0 to 1, this will be set. Writing 1 to this bit will clear it. DSP Clock Enable CKEN 0: DSP CLK=DC (LOW), 1: Enable DSP CLK. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 99 2007-1-29...
Page 101 0: asserts IRQ2- to DSP core to interrupt DSP by RISC DSP Boot MODE 0 0 Reserved BOOTM 0 1 Reserved 1 0 HIP boot 1 1 No boot, start at 0x000h from internal IPM Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 100 2007-1-29...
Page 102: Media Hardware Accelerator (Mha)
ATJ2135 PROGRAMMING GUIDE Media Hardware Accelerator (MHA) 12.1 Description MHA (Media Hardware Accelerator) is a coprocessor for image or video processing. It supports the following processing: DCT (Discrete Cosine Transform), IDCT (Inverse DCT), Q (Quantization), IQ (Inverse Q), IDRO (Input Data Reorder), ODRO (Output Data Reorder), LS (Level Shift) and ILS (Inverse Level Shift).
Page 103: Register List And Memory Map
MHA Control Register. Before setting RST bit, MHA clock shall be enabled. Offset=0x0000 Table 101: MHA_CTL Bit Field Description Name Description R/W Reset MHA enable. This bit also controls the mapping of Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 102 2007-1-29...
Page 104: Table 102: Q Table Mapping
The two blocks is used in turn, so MCU and MHA can work at the same time. Table 103: B1/B2 Mapping Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 103 2007-1-29...
Page 105: Mha_Cfg
01 select table1. 10 select table 2. 11 select table 3. Table select for block 3. 23:22 QTABS3 00 select table 0. 01 select table1. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 104 2007-1-29...
Page 106 1 Current frame is intra frame. Sample Precision. 0 8bit per pixel sample 1 9bit per pixel sample Zigzag Scan order is selected. 0 normal order 1 Zigzag Scan order Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 105 2007-1-29...
Page 107: Mha_Dcscl01
15:12 Reserved 11:0 DCSCL2 Intra DC coefficient Scalar for block 2. 12.2.5 MHA_DCSCL45 MHA intra DC coefficient Scalar Register of block 5 and block 4. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 106 2007-1-29...
Page 108: Mha_Dcscl67
MHA other coefficient Scalar for block 1 and block 0 Offset=0x0018 Table 109: MHA_QSCL Bit Field Description Name Description Default 31:12 Reserved 11:0 QSCL0 Other coefficient Scalar for block 0 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 107 2007-1-29...
Page 109: Motion Compensation Accelerator (Mca)
ATJ2135 PROGRAMMING GUIDE Motion Compensation Accelerator (MCA) 13.1 Description MCA (Motion Compensation Accelerator) is applied to the interpolation process of the motion compensation in inter block decoding process of WMV, which is required by progressive P frame and B frame decoding. It accepts various types of pixel blocks from the reference frame in progressive mode to produce 8x8 or 16x16 interpolated block based on WMV interpolation technology.
Page 110: Mca_Ctl
Includes the two lowest bits of MVx and MVy of motion vector. The format is (MVy[1:0] || MVx[1:0]). MCA_B1 and MCA_B2 mapped control Table MCA_B1 and MCA_B2 Mapping B_MAP[1:0] MCA_B1 MCA_B2 Mapping Mapping BMAP Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 109 2007-1-29...
Page 111 MCA. MCA Start. MCA will start if write 1 to this bit. After it STAR completes, this bit will be cleared by hardware. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 110 2007-1-29...
Page 112: Nand Flash Interface
NAND FLASH device is hung up. ATJ2135 has a voltage selection PIN: NF_VP, if the PIN is connected to VDD, it can support 1.8v NAND FLASH device; if the PIN is connected to VCC, it can support 3.3v NAND FLASH device.
Page 113: Nand_Ctl
DMA Block Mode enable BLOC 0: demand 1: block Reserved RW wait. WAIT Bit WR wait cycles 0: 4 CLK, 1: 8 CLK. VPDE NF_VP Detect circuit Enable. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 112 2007-1-29...
Page 114 CE0-_ENB. Nand FLASH access on Bank 1, ie. CE0-. 1 enable. CE0E The interface allows to 1 external NAND FLASH device. The chip enable select field decodes to select one of the 1 external Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 113 2007-1-29...
Page 115: Nand_Status
Nand FLASH State Machine transfer complete interrupt has occurred. Writing 1 to this bit will clear it. Hardware will automatically clear this bit when MCU sends the next command. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 114 2007-1-29...
Page 116: Nand_Fifotim
ALE single to low. If it is necessary to make Timing by StateMachine, be sure that this bit must be written to zero. Timing Control. TCTL 1: Controlled by MCU 0: Controlled by State Machine. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 115 2007-1-29...
Page 117: Nand_Clkctl
1: FLASH R-/W- high Level wait. 14.2.5 NAND_BYTECNT Byte Counter Register Offset=0x0010 Table 120: NAND_BYTECNT Bit Field Description Name Description Reset 31:14 Reserved 13:0 BYTECNT BYTE COUNTER[13:0] Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 116 2007-1-29...
Page 118: Nand_Addrlo1234
14.2.8 NAND_ ADDRHI1234 FLASH Address high Register1234 Offset=0x001C Table 123: NAND_ ADDRHI1234 Bit Field Description Name Description Reset 31:24 ADDRHI4 FLASH address4[15:8] 23:16 ADDRHI3 FLASH address3[15:8] Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 117 2007-1-29...
Page 119: Nand_ Addrhi56
USER DATA Byte3 23:16 DATA2 USER DATA Byte2 15:8 DATA1 USER DATA Byte1 DATA0 USER DATA Byte0 14.2.11 NAND_BUF1 User Data Area Buffer 1 Register Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 118 2007-1-29...
Page 120: Nand_Cmd
RW 0 1: State Machine sent DATA wait RBI ready. Address Cycle Selection. 20:18 ADDRCYCLE Address cycle select. RW 0 0 0 0 0 cycle Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 119 2007-1-29...
Page 121: Table 128: Nand_Cmd (Spare Mode) Bit Field Description
CMD_Mode_Sel. 00:general mode; 31:30 MODE 01:spare mode; 1x: reserved Sequent CMD. SEQU 0: No Sequent CMD;1: Sequent CMD Dual Channel Enable. DUAL 1: Dual channel, 0: normal Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 120 2007-1-29...
Page 122 （ 512 or 256 ） *1 23:20 ADDROFFSET256 0001 （ 512 or 256 ） *2 0010 （ 512 or 256 ） *3 0011 （ 512 or 256 ） *4 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 121 2007-1-29...
Page 123: Nand_Eccctl
Read-Solomon ECC Error. 0 means less than 3 symbols Error are RSL4 detected and can be corrected. 1 means more than 3 symbols Error are detected. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 122 2007-1-29...
Page 124: Nand_Hamecc0
1 0 enable Read Solomon Code ECC, disable Hamming Code ECC. 1 1 reserved. 14.2.14 NAND_HAMECC0 Hamming ECC Register0 Offset= 0x0034 Table 130: NAND_HAMECC0 Bit Field Description Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 123 2007-1-29...
Page 125 HM_ECC1 4 H14E HM_ECC1’4 Even Bit HM_ECC1 3 H13E HM_ECC1’3 Even Bit HM_ECC1 2 H12E HM_ECC1’2 Even Bit HM_ECC1 1 H11E HM_ECC1’1 Even Bit HM_ECC1 0 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 124 2007-1-29...
Page 126: Nand_Hamecc1
HM_ECC2’6 Even Bit HM_ECC2 5 H25E HM_ECC2’5 Even Bit HM_ECC2 4 H24E HM_ECC2’4 Even Bit HM_ECC2 3 H23E HM_ECC2’3 Even Bit HM_ECC2 2 H22E HM_ECC2’2 Even Bit Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 125 2007-1-29...
Page 127: Nand_Hamecc2
HM_ECC3’4 Even Bit HM_ECC3 3 H33E HM_ECC3’3 Even Bit HM_ECC3 2 H32E HM_ECC3’2 Even Bit HM_ECC3 1 H31E HM_ECC3’1 Even Bit HM_ECC3 0 H30E HM_ECC3’0 Even Bit Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 126 2007-1-29...
Page 128: Nand_Hamcec
Err Value bit, the Error Value is to be E (x) with the data at the Error Location. This field is only valid when the Ready flag is set. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 127 2007-1-29...
Page 129: Nand_Rse1
This field is only valid when the Ready flag is set. 14.2.20 NAND_RSE2 RS ECC E(x) Register2 Offset=0x004C Table 136: NAND_RSE2 Bit Field Description Name Description Reset 31:24 YI2HI Yi2[15:8] Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 128 2007-1-29...
Page 130: Nand_Rse3
This field is only valid when the Ready flag is set. 14.2.22 NAND_RSPS0 This Register provides a read only view of 9 bytes parity. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 129 2007-1-29...
Page 131: Nand_Rsps1
23:16 RSP6 Parity[55:48] 0FFh 15:8 RSP5 Parity[47:40] 0FFh RSP4 Parity[39:32] 0FFh 14.2.24 NAND_RSPS2 RS ECC Parity Symbols Register2 Offset=0x005C Table 140: NAND_RSPS2 Bit Field Description Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 130 2007-1-29...
Page 132: Nand_Fifodata
Busy_Timeout flag. OUTF 1: timeout 0: normal Busy_Timeout_ENA bit. Setting this bit to 1 enables the OUTE busy timeout of the state machine and counter. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 131 2007-1-29...
Page 133: Sd/Mmc Interface
SD MMC CRC7 register SD_RSPBUF0 0x001c SD MMC RSP Buffer0 (Bit31~0) register SD_RSPBUF1 0x0020 SD MMC RSP Buffer1 (Bit63~32) register SD_RSPBUF2 0x0024 SD MMC RSP Buffer2 (Bit95~64) register Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 132 2007-1-29...
Page 134: Sd_Ctl
Reserved SD Interface Data Width select 00b: 1bit DATAWID 01b: 4bit 10b: 8bit 11b: Reserved 15.2.2 SD_CMDRSP SD MMC Card CMD Response Control Register Offset=0x0004 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 133 2007-1-29...
Page 135: Sd_Rw
Write “1” to start State machine, and auto cleared when it finishes. Bit 0 shows the Responds received or not. 15.2.3 SD_RW SD MMC Card Read or Write Operation Control Register Offset=0x0008 Table 147: SD_RW Bit Field Description Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 134 2007-1-29...
Page 136: Sd_Fifoctl
CRC16 buffer when read device. 15.2.4 SD_FIFOCTL SD MMC FIFO Controller Registers Offset=0x000C Table 148: SD_FIFOCTL Bit Field Description Name Description Reset 31:11 Reserved Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 135 2007-1-29...
Page 137: Sd_Cmd
SD MMC Card Send Command Register Offset=0x0010 Table 149: SD_CMD Bit Field Description Name Description Reset 31:8 Reserved Command register. Fixed bit7 is 0 01xxxxxxb The bit6 is 1 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 136 2007-1-29...
Page 138: Sd_Arg
Table 152: SD_RSPBUF0 Bit Field Description Name Description Reset 31:0 RSP0 Bit31~0 15.2.9 SD_RSPBUF1 SD MMC RSP Buffer1 (Bit63~32) Register Offset=0x0020 Table 153: SD_RSPBUF1 Bit Field Description Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 137 2007-1-29...
Page 139: Sd_Rspbuf2
SD MMC RSP Buffer4 (Bit135~128) Register Offset=0x002C Table 156: SD_RSPBUF4 Bit Field Description Name Description Reset 31:8 Reserved RSP 4 Bit135~128 15.2.13 SD_DAT SD MMC DATA Register Offset=0x0030 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 138 2007-1-29...
Page 140: Sd_Clk
0: Auto cleared when send clock over 15.2.15 SD_BYTECNT SD Byte Counter Offset=0x0038 Table 159: SD_BYTECNT Bit Field Description Name Description Reset 31:16 Reserved 15:0 BYTECNT Byte Count Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 139 2007-1-29...
Page 141: Yuv2Rgb Interface
ATJ2135 PROGRAMMING GUIDE YUV2RGB Interface 16.1 Description The Module performs image data transfer from frame buffer to LCD panel. It accelerates the frame data display by hardware operation. It is optional and mainly used in movie decoding. The processes include: 1.
Page 142: Table 162: Yuv2Rgb_Ctl Bit Field Description
001:18bit (RGB 666 1transfer) 010:8bit (RGB 565 2transfer) 13:11 FORMATS 011:9bit (RGB 666 2transfer) 100: 8bit (RGB 888 3transfer) 101:6bit (RGB 666 3transfer) 110: Reserved 111: Reserved Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 141 2007-1-29...
Page 143 Note: When RGB decoder destination (Bit15) selects LCD interface, LCD color depth can select RGB565, RGB666 and RGB888 format. When RGB decoder destination selects frame buffer, LCD color depth can only select Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 142 2007-1-29...
Page 144: Yu2Rgb_Dat
Divide from 1~128 16.2.4 YUV2RGB_FrameCount YUV2RGB Frame Count Register Offset=0x000c Table 165: YUV2RGB_FrameCount Bit Field Description Name Description Reset 31:17 Reserved 16:8 FCOLC Frame Column Counter. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 143 2007-1-29...
Page 146: Usb2.0 Sie
ATJ2135 PROGRAMMING GUIDE USB2.0 SIE 17.1 General Description AS 7605 USB2.0 device controller is fully compliant with the Universal Serial Bus 2.0 specification. This high performance USB2.0 device controller integrates USB transceiver, SIE, and provides multifarious interfaces for generic MCU, RAM, ROM and DMA controller. So it is suitable for a variety of peripherals, such as: scanners, printers, mass storage devices, and digital cameras.
Page 147: I2C (2) Interface
18.1 Description ATJ2135 has two I2C Interfaces, which can be configured as either master or slave device. In master mode, it generates the clock (I2C_SCL) and initiates transactions on the data line (I2C_SDA). Data on the I2C bus is byte-oriented. Multi-Master mode cannot support 10bit address and hi-speed mode.
Page 148: I2Cx_Ctl
Generating Bus Control Condition (only for master mode). 00: No effect 3:2 GBCC 01: Generating START condition 10: Generating STOP condition 11: Generating Repeated START condition Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 147 2007-1-29...
Page 149: I2Cx_Clkdiv
(400kbps) mode. Calculating SCL is as follows: SCL=PCLK/(CLKDIV*16) 18.2.3 I2Cx_STAT I2Cx Status Register Offset=0x0008 Table 170: I2Cx_STAT Bit Field Description Name Description Reset 31:8 Reserved Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 148 2007-1-29...
Page 150 0: Indicate the last byte received or transmitted is address IRQ Pending Bit. Writing 1 to this bit will clear it. IRQP 1: IRQ 0: No IRQ Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 149 2007-1-29...
Page 151: I2Cx_Addr
In slave mode, the bit is slave address match bit. 0: Not match, do not send the IRQ 1: Match, l send IRQ to MCU 18.2.5 I2Cx_DAT I2Cx Data Register Offset=0x0010 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 150 2007-1-29...
Page 152: Table 172: I2Cx_Dat Bit Field Description
ATJ2135 PROGRAMMING GUIDE Table 172: I2Cx_DAT Bit Field Description Name Description Reset 31:8 Reserved TXRXDAT Transmit/Receive Data. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 151 2007-1-29...
Page 153: Uart Interface
ATJ2135 PROGRAMMING GUIDE UART Interface 19.1 Description ATJ2135 contains UART interface and it has the following features: 5-8 Data Bits and LSB first in transmitting and receiving. 1-2 stop bits Even, Odd, or No Parity 8-byte transmit and receive FIFO...
Page 154: Uart2_Ctl
TX/RX FIFO Select. TX/RX FIFO Level is reflected in bit 15 to bit 12 of TRFS UART2_STAT Register. 0: RX FIFO 1: TX FIFO Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 153 2007-1-29...
Page 155 1, 2 stop bits are generated. The receiver always checks 1 stop bit only. Data Width Length Select. 00: 5bit DWLS 01: 6bit 10: 7bit 11: 8bit Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 154 2007-1-29...
Page 156: Uart2_Rxdat
7:0 bits is the data. 19.2.4 UART2_STAT UART2 Status Register Offset=0x000c Table 178: UART2_STAT Bit Field Description Bit Name Description R/W Reset 31:16 Reserved Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 155 2007-1-29...
Page 157 Writing 1 to the bit to clear the bit. UART2/IR RX IRQ Pending Bit. 0: No IRQ 1: IRQ Writing 1 to the bit to clear it. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 156 2007-1-29...
Page 158: Ir Interface
IrDA 1.1 with error detection UART2_CLKDIV 20.2 Register List Table 180: IR Registers Block Base Address Block Name Physical Bass Address KSEG1 Base Address 0x10160000 0xB0160000 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 157 2007-1-29...
Page 159: Ir_Pl
Name Description R/W Reset 31:13 Reserved Current Received Bytes Number (only used in MIR or FIR mode). 12:0 CRXBN Writing the field to reset it. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 158 2007-1-29...
Page 160: Key Scan
ATJ2135 PROGRAMMING GUIDE Key Scan 21.1 Description The Key Scan supports parallel mode and serial mode. The max scan matrix is 16x8. The key scan data FIFO is 4 levels (4*32). In parallel mode, the max scan matrix is 3x3 and is showed as follows:...
Page 161: Figure 12: 8*8 Key Scan Matrix In Serial Mode
Figure 12: 8*8 Key Scan Matrix in Serial Mode Note: KEYSO is PIN KEYO1, KEYSCLK is PIN KEYO0. One line Scan timing: the line 7 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 160 2007-1-29...
Page 162: Figure 13: One Line Scan Timing
Figure 14: The Whole Key Scan Timing In the serial mode, two external 8bit shift registers can be used at last, that is to say, the maximum scan matrix is 8x16. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 161 2007-1-29...
Page 163: Register List
Key Scan IRQ Pending Bit. 0: No IRQ 1: IRQ Writing 1 to the bit will clear the bit. Key Scan IRQ Enable. IREN 0: Disable 1: Enable Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 162 2007-1-29...
Page 164: Key_Dat0
Key Scan Enable. 0: Disable 1: Enable 21.2.2 KEY_DAT0 Key Scan Data Register0 Offset=0x0004 Table 187: KEY_DAT0 Bit Field Description Name Description Reset 31:0 Key Scan Data Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 163 2007-1-29...
Page 165: Key_Dat1
Reset 31:0 Key Scan Data 21.2.5 KEY_DAT3 Key Scan Data Register3 Offset=0x0010 Table 190: KEY_DAT3 Bit Field Description Name Description Reset 31:0 Key Scan Data Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 164 2007-1-29...
Page 166: Gpio And Multi-Function Configuration
Description 22.1.1 GPIO/Function Pin There are 64 bit General purpose IO ports in ATJ2135. Each GPIO is controlled by the corresponding bit in GPIOx_Out_En register and GPIOx_In_En register. GPIO shares pads with many functional pads. The GPIO function enjoys the highest priority, which means if GPIO enables input or output, the corresponding functional signal is masked.
Page 167: Register List
GPIOA[31:0] Output Enable. 31:0 OUTEN 0: Disable 1: Enable 22.2.2 GPIO_AINEN GPIOA Output Enable Register Offset=0x0004 Table 194: GPIO_AINEN Bit Field Description Name Description Reset Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 166 2007-1-29...
Page 168: Gpio_Adat
22.2.5 GPIO_BINEN GPIOB Output Enable Register Offset=0x0010 Table 197: GPIO_BINEN Bit Field Description Name Description Reset GPIOB [31:0] Input Enable. 31:0 INEN 0: Disable 1: Enable Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 167 2007-1-29...
Page 169: Gpio_Bdat
24:22 GPIOA[2:0] 010: RGB_RS, WD9, WD0 011: reserved 100: SD_CMD, reserved CEB6 Multi-function. 00: reserved 21:20 CEB6 01: reserved 10: RGB_CE 11: SDCLK 19:16 Reserved Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 168 2007-1-29...
Page 170: Gpio_Mfctl1
NAND_D[7:0] Multi-function. 001: NandFlash_D[7:0] NAND_D[7:0] 010: RGB_WD[17:10] Others: Reserved NAND_D[15:8] Multi-function. 001: NandFlash_D[15:8] NAND_D[15:8] 010: RGB_WD[8:1] 100: SD_D[7:0] Others: Reserved 22.2.8 GPIO_MFCTL1 Multi-function Control Register1 Offset=0x001c Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 169 2007-1-29...
Page 171: Table 200: Gpio_Mfctl1 Bit Field Description
Others: reserved Pad Enables by MFEN. UART2 TX and RX Multi-function. 0: UART_TX and UART_RX U2TR 1: I2C2_SCL and I2C2_SDA Pad Enables by MFEN. Reserved Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 170 2007-1-29...
Page 172: Pad_Drv
DRWE P_SDRWEB RW 1 DRCA P_SDRCASB RW 1 DRRA P_SDRRASB RW 1 Reserved RW 0 A5_0 P_A[5:0] RW 0 P_CE[5:3],P_CE0 RW 0 Reserved RW 0 Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 171 2007-1-29...
Page 174: Dac And Headphone Driver
ATJ2135 PROGRAMMING GUIDE DAC and Headphone Driver 23.1 Description ATJ2135’s internal DAC is an on-chip Sigma-Delta Modulator of which an 18-bit high performance DAC is composed. DAC interface supports 8-level play back FIFO (16 X 24bit data channel variable sample...
Page 175: Register List
Register List Table 202: DAC Registers Block Base Address Module Name Physical Bass Address KSEG1 Base Address 0x10100000 0xB0100000 Table 203: DAC Registers Offset Address Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 174 2007-1-29...
Page 176: Dac_Ctl
DIEN 0: Disable 1: Enable Internal DAC Quantization Levels. 15:12 QUL Levels=[3*(22+QUL[3:0])]/64, 1001 Default levels=3*27/64=1.27 Internal DAC Quantization Bit Select. QUBS 0: 2bit 1: 1bit Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 175 2007-1-29...
Page 177: Dac_Fifoctl
0: Left 1: Right DAC FIFO Debug Data Ready Flag. 0: Not Ready DDRF 1: Ready After DAC_DAT_Debug is read, the bit is automatically cleared. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 176 2007-1-29...
Page 178 1: Enable Reserved DAC FIFO Input Select. 00: APB FINS 01: Reserved 10: Reserved 11: ADC DAC FIFO Reset. FIRT 0: Reset FIFO 1: Enable FIFO Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 177 2007-1-29...
Page 179: Dac_Dat
Reserved 23.2.5 DAC_Analog DAC Analog Register Offset=0x0010 Table 208: DAC_Analog Bit Field Description Name Description R/W Reset Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 178 2007-1-29...
Page 180 Total 32 level, -1.8Db/step PA Gain Control. PAGC 0: 1.2 Vpp 1: 1.6 Vpp Internal Analog Mixer and PA Enable. AMPE 0: Disable 1: Enable Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 179 2007-1-29...
Page 182: Adc
ADC Data Register 0x000c ADC_Analog ADC Analog Register 0x0010 ADC_Debug ADC Debug Register 24.2.1 ADC_CTL ADC Control Register Offset=0x0000 Table 211: ADC_CTL Bit Field Description Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 181 2007-1-29...
Page 183 100: -1.5db 101: 0db 110: 1.5db 111: 3.0db FM Right Channel Enable. FMRE 0: Disable 1: Enable FM Left Channel Enable. FMLE 0: Disable 1: Enable Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 182 2007-1-29...
Page 184: Adc_Fifoctl
1: ADC Clock from OSC (For Debug) 24.2.2 ADC_FIFOCTL ADC FIFO Control Register Offset=0x0004 Table 212: ADC_FIFOCTL Bit Field Description Name Description Reset 31:11 Reserved Reserved Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 183 2007-1-29...
Page 185: Adc_Dat
ADC FIFO Input Select. FINS 0: ADC 1: Reserved ADC FIFO Reset. FIRT 0: Reset FIFO 1: Enable FIFO 24.2.3 ADC_DAT ADC FIFO Data Register Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 184 2007-1-29...
Page 186: Adc_Analog
000: 0 level 001: 1 level 010: 2 level 11:9 OPAD2CS 011: 3 level 100: 4 level 101: 5 level 110: 6 level 111: 7 level Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 185 2007-1-29...
Page 187: Adc_Debug
111: 7 level 24.2.5 ADC_Debug ADC Debug Register Offset=0x0010 Table 215: ADC_Debug Bit Field Description Name Description Reset 31:23 Reserved DEDF ADC Debug Data Channel Flag. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 186 2007-1-29...
Page 188 ATJ2135 PROGRAMMING GUIDE ADC Debug Ready Flag. 0: Not Ready DERF 1: Ready Writing 1 to the bit will clear it. 20:0 DEDAT ADC Debug Data. Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 187 2007-1-29...
Page 189 ATJ2135 PROGRAMMING GUIDE Appendix 25.1 Acronym and Abbreviations ADC: Analog-to-Digital Converter AHB: Advance High-Performance Bus ALE: Address-Locked Enable APB: Advance Peripheral Bus ATA: Advance Technology Attachment BIST: Build-in Self-Test CLE: Command-Locked Enable CMU: Clock Management Unit CP0: System Control Coprocessor...
Page 190 PAL: Phase Alteration Line PCM: Pulse Code Modulation PFM: Pulse Frequency Modulation PLL: Phase-Locked Loop PMU: Power Management Unit PWM: Pulse Width Modulation RISC: Reduced Instruction Set Computing Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 189 2007-1-29...
Page 191 SW: Software THD: Total Harmonic Distortion TLB: Translation Look-aside Buffer TS: Transport Stream UART: Universal Asynchronous Receiver Transmitter WMA: Windows Media Audio WMV: Windows Media Video Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 190 2007-1-29...
Page 192 Address: Bldg. 15-1, NO.1, HIT Rd., Tangjia, Zhuhai, Guangdong, China Tel: +86-756-3392353 Fax: +86-756-3392251 Post code: 519085 http://www.actions-semi.com Business Email: mp-sales@actions-semi.com Technical Service Email: mp-cs@actions-semi.com Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved. Ver 1.1 Page 191 2007-1-29...

Actions ATJ2135 Programming Manual

1 Introduction

2 Pin Description

3 Functional Block and Memory Map

4 Clock Management Unit (CMU)

5 Interrupt Controller

6 PMU/DC-DC Converter

32 BIT RISC Core

8 SDRAM Interface

9 SRAM on Chip

10 Dma/Bus Arbiter

24 BIT DSP Core

12 Media Hardware Accelerator (MHA)

13 Motion Compensation Accelerator (MCA)

14 NAND FLASH Interface

Quick Links

Summary of Contents for Actions ATJ2135